Based on SSTC spec (1):
"If the stimecmp (supervisor-mode timer compare) register is implemented, STIP is read-only in mip and reflects the supervisor-level timer interrupt signal resulting from stimecmp. This timer interrupt signal is cleared by writing stimecmp with a value greater than the current time value."
This fixes operation in Spike with SSTC extension enabled, e.g.
$ spike --isa RV64IMAFDCH_zicntr_zihpm_sstc[1]. https://tools.cloudbear.ru/docs/riscv-sstc-0.5.4-20211013.pdf