riscv: Fix SSTC extension support

From the SSTC spec:
"If the stimecmp (supervisor-mode timer compare) register is implemented,
then STIP is read-only in mip and reflects the supervisor-level timer
interrupt signal resulting from stimecmp. This timer interrupt signal
is cleared by writing stimecmp with a value greater than the current time
value."

This fixes operation in Spike with sstc extension enabled.
Example:

spike --isa RV64IMAFDCH_zicntr_zihpm_sstc

Reviewed by: mhorne
Differential Revision: https://reviews.freebsd.org/D45226

(cherry picked from commit ddd0d4f4cd65341a07bb3bb833dee7982018fd60)