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arm64/disassem.c: Add shifted register definitions with ror
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Authored by koliagogsadze_gmail.com on Jun 1 2023, 9:20 PM.
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mhorne
andrew
manu
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rG7b1b44551ff9: arm64/disassem.c: Add shifted register definitions with ror
rG9aef25d2686b: arm64/disassem.c: Add shifted register definitions with ror
Summary

Add disassembly support for the following shifted register instructions:

  • mvn
  • orn
  • orr
  • and
  • ands
  • bic
  • bics
  • eon
  • eor
  • tst

According to Arm64 documenation, operational pseuducode of shifted
register instruction must return UNDEFINED if shift type is RESERVED
('11'). Hence, removed "rsv" from shift_2 array and added "ror".
In case of shift type is 4 and this type is RESERVED,
we will return undefined.

Test Plan

https://github.com/toor1245/freebsd-src/pull/2

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rG FreeBSD src repository
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Buildable 51995
Build 48886: arc lint + arc unit

Event Timeline

koliagogsadze_gmail.com created this revision.Jun 1 2023, 9:20 PM
Herald added a reviewer: manu. · View Herald TranscriptJun 1 2023, 9:20 PM
Herald added subscribers: emaste, imp. · View Herald Transcript
koliagogsadze_gmail.com requested review of this revision.Jun 1 2023, 9:20 PM
Harbormaster completed remote builds in B51851: Diff 122741.Jun 1 2023, 9:20 PM
koliagogsadze_gmail.com edited the test plan for this revision. (Show Details)Jun 1 2023, 9:21 PM
koliagogsadze_gmail.com added a comment.Jun 1 2023, 9:44 PM

refs:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/MVN--Bitwise-NOT--an-alias-of-ORN--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ORN--shifted-register---Bitwise-OR-NOT--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ORR--shifted-register---Bitwise-OR--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/AND--shifted-register---Bitwise-AND--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ANDS--shifted-register---Bitwise-AND--shifted-register---setting-flags-
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/BIC--shifted-register---Bitwise-Bit-Clear--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/BICS--shifted-register---Bitwise-Bit-Clear--shifted-register---setting-flags-
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/EON--shifted-register---Bitwise-Exclusive-OR-NOT--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/EOR--shifted-register---Bitwise-Exclusive-OR--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/TST--shifted-register---Test--shifted-register---an-alias-of-ANDS--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/MOV--register---Move--register---an-alias-of-ORR--shifted-register--?lang=en

mhorne added inline comments.Jun 9 2023, 4:24 PM
sys/arm64/arm64/disassem.c
492

I think it is slightly better named as has_shift_ror.

mhorne accepted this revision.Jun 9 2023, 4:24 PM

LGTM otherwise.

This revision is now accepted and ready to land.Jun 9 2023, 4:24 PM
koliagogsadze_gmail.com updated this revision to Diff 123067.EditedJun 11 2023, 12:44 AM

Changed is_shift_ror to has_shift_ror and fixed check shift type.
For testing RESERVED case (shift == 3) I added instruction manually

.macro ADDS_SHIFT_RSV_64 xd, xn, xm, shift, imm
	.inst	((0b10101011 << 24) | (\shift << 22) | \
		(0b0 << 21) 	    | (\xm << 16)    | \
		(\imm << 10)	    | (\xn << 5)     | \
		(\xd << 0))
.endm

# adds	x0, x1, x3, RESERVED #1
ADDS_SHIFT_RSV_64 0, 1, 3, 3, 1

ref: https://github.com/toor1245/freebsd-src/pull/2/files

This revision now requires review to proceed.Jun 11 2023, 12:44 AM
Harbormaster completed remote builds in B51995: Diff 123067.Jun 11 2023, 10:17 PM
mhorne accepted this revision.Jun 17 2023, 3:30 PM
This revision is now accepted and ready to land.Jun 17 2023, 3:30 PM
Closed by commit rG9aef25d2686b: arm64/disassem.c: Add shifted register definitions with ror (authored by koliagogsadze_gmail.com, committed by mhorne). · Explain WhyJun 17 2023, 4:20 PM
This revision was automatically updated to reflect the committed changes.
mhorne added a commit: rG9aef25d2686b: arm64/disassem.c: Add shifted register definitions with ror.
mhorne added a commit: rG7b1b44551ff9: arm64/disassem.c: Add shifted register definitions with ror.Jul 7 2023, 7:25 PM

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sys/arm64/arm64/disassem.c

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