Ingenic CPUs treat plain cache writeback as local-only operation and do
nothing if that is a remote CPU that holds the dirty cache line. They
do broadcast invalidate and write-and-invalidate to other cores though,
so take advantage of that and use wbinv in place of wb as this still gives
us required busdma semantics. Otherwise we'd have to do IPI to remote CPU
ourselves.
Details
Details
world-bench on Creator CI20 with DMA enabled.
Diff Detail
Diff Detail
- Repository
- rS FreeBSD src repository - subversion
- Lint
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Tests Skipped - Build Status
Buildable 6425
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I don't see anything wrong with this change other then needing a rebase, but am not an expert on these issues.