Page MenuHomeFreeBSD

Use mips_dcache_wbinv_range instead of mips_dcache_wb_range on CPU_XBURST
Needs ReviewPublic

Authored by kan on Dec 28 2016, 3:43 PM.

Details

Reviewers
jmcneill
adrian
br
Group Reviewers
MIPS
Summary

Ingenic CPUs treat plain cache writeback as local-only operation and do
nothing if that is a remote CPU that holds the dirty cache line. They
do broadcast invalidate and write-and-invalidate to other cores though,
so take advantage of that and use wbinv in place of wb as this still gives
us required busdma semantics. Otherwise we'd have to do IPI to remote CPU
ourselves.

Test Plan

world-bench on Creator CI20 with DMA enabled.

Diff Detail

Repository
rS FreeBSD src repository - subversion
Lint
Lint Skipped
Unit
Unit Tests Skipped
Build Status
Buildable 6425

Event Timeline

kan retitled this revision from to Use mips_dcache_wbinv_range instead of mips_dcache_wb_range on CPU_XBURST.
kan updated this object.
kan edited the test plan for this revision. (Show Details)
kan added reviewers: adrian, br, MIPS.
kan set the repository for this revision to rS FreeBSD src repository - subversion.

I don't see anything wrong with this change other then needing a rebase, but am not an expert on these issues.