Tested by hand in SMP environment. Works stable. No testsuite available for RISC-V yet due to missing C plus plus
N.B. There is no floating point exception traps on RISC-V.
N.B. No flq, fsq (for quad access) instructions supported yet by GCC 6.1
Differential D8529
Full softfloat and hardfloat support for RISC-V br on Nov 15 2016, 4:57 PM. Authored by Tags None Referenced Files
Details
Tested by hand in SMP environment. Works stable. No testsuite available for RISC-V yet due to missing C plus plus N.B. There is no floating point exception traps on RISC-V.
Diff Detail
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