PCIe interfaces of Marvell SoCs are separate and not linked together
in a bus, so if there is more than one PCIB device it is necessary
to set an appropriate bus number from which actual enumeration should
start.
Submitted by: Marcin Mazurek <mma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision:
Reviewed by: