fix-up for configuration of AMD Family 10h processors borrowed from Linux

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Summary

http://lxr.free-electrons.com/source/arch/x86/kernel/cpu/amd.c#L643

[kib]

sys/amd64/amd64/initcpu.c

87 ↗

(On Diff #15491)

Is CD == Cache Disabled ? We and Intel usually call the mode UC (uncaheable).

Also, I do not understand the reference to 'guest VMs' in the comment. Is this about bhyve ? IMO the normal behaviour for the drivers would be suboptimal, most important.

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sys/amd64/amd64/initcpu.c

87 ↗

(On Diff #15491)

Is CD == Cache Disabled ? We and Intel usually call the mode UC (uncaheable).

It's indeed Cache Disabled, but AMD64 Architecture Programmer's Manual, Volume 2: System Programming[1] documents both UC and CD and says (in section 7.4):

The CD memory type is a form of uncacheable memory type that occurs
when caches are disabled (CR0.CD=1). With CD memory, it is possible for the address to be
cached due to an earlier cacheable access, or due to two virtual-addresses aliasing to a single
physical address.

Also, I do not understand the reference to 'guest VMs' in the comment. Is this about bhyve ? IMO the normal behaviour for the drivers would be suboptimal, most important.

I guess that it is about any guest that uses Nested Paging and that includes bhyve.
I do not think that WC+ type can be set on host-only pages, it seems that that type emerges internally for certain combination of guest and host memory types. That's described in section 15.25.8 of the same document. So, I am not sure how this could affect the drivers.

All that said, I am not an expert in this area, I just picked up something that I noticed in the Linux code.

[1] Publication No. 24593 Revision 3.23

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Adding people who might have more insights into AMD SVM.

[grehan]

Anish knows SVM :)

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I am going to commit this unless anyone explicitly objects.