Migrate all PowerPC QorIQ to the sdhci_fsl_fdt SDHC driver. There are a
few differences that need to be accounted for:
- On PowerPC device trees, the clock-frequency property defines the clock rate, not a clocks reference property.
- On some older SoCs (32-bit only?) the BURST fields of the WML register are reserved, and must be 0x10, so add a FSL quirk (errata field) to account for this.
- The PowerPC eSDHC controllers must have the DMA SNOOP bit set for DMA to work properly and avoid corruption.
As part of this, make the fallback "fsl,esdhc" compat data work for
PowerPC. If these fallbacks are not compatible with ARM SoCs, newer
compat strings could be added for those, but the conservative catch-all
should work for most SoCs, though perhaps less optimal.
Assisted-by: Claude Code (Opus 4.7(1M))