Add an unsupported-config guard rejecting nrxqsets > ntxqsets, and
teach the P5+ NQ datapath to handle the opposite asymmetric case:
extra Tx rings beyond the Rx ring count. softc->nq_rings[i].type now
tags each NQ as SHARED_NQ (paired with an Rx CQ) or BNXT_TX_ONLY_NQ
(dedicated to an extra Tx CQ with no backing Rx ring); bnxt_init()
and bnxt_hwrm_resource_free() gate all Rx ring group/ring/stat-ctx
alloc and free on IS_SHARED_NQ() so the extra Tx-only NQs don't touch
nonexistent Rx ring state. Gate the new type-tagging and IS_SHARED_NQ
checks on BNXT_CHIP_P5_PLUS(), since non-P5+ chips never allocate
softc->nq_rings and would otherwise access a nonexistent array.
BNXT_TX_ONLY_NQ is a distinct value from the existing MPC-private
TX_CP_NQ; the two are unrelated and kept apart to avoid confusion.
Suggested by: Drew Gallatin