amd64: enable EFER.TCE

[alc]

Summary

This option tells AMD processors that targeted TLB invalidation instructions, such as invlpg, only have to invalidate page walk cache entries along the path to the targeted virtual address. Since we have long issued TLB invalidation operations before freeing any page table pages, this option should be safe for use with the amd64 pmap.

[alc]

dougm@ has been running stress on a Ryzen processor for more than 24 hours, and seen no ill effects.

[kib]

It would be useful to provide a reasoning why the setting is safe.

From my understanding, there are (at least) two situations where TCE would be unsafe:

1. Recursive pt mapping. But when we modify the kernel page table in a way that modifies the paging structure above the lowest level, we also explicitly invalidate the recursive mapping, in pmap_remove_kernel_pde(), pmap_demote_pde(), pmap_demote_pdpe().
2. Sharing page table pages, mostly relevant when sharing occurs not at the leafs of the page table radix tree. We do not do that at all.

Anything else I missing?

[alc]

In D51093#1166331, @kib wrote:

It would be useful to provide a reasoning why the setting is safe.

From my understanding, there are (at least) two situations where TCE would be unsafe:

1. Recursive pt mapping. But when we modify the kernel page table in a way that modifies the paging structure above the lowest level, we also explicitly invalidate the recursive mapping, in pmap_remove_kernel_pde(), pmap_demote_pde(), pmap_demote_pdpe().
2. Sharing page table pages, mostly relevant when sharing occurs not at the leafs of the page table radix tree. We do not do that at all.

Anything else I missing?

No, I don't think that you are missing anything.