nvme: Fix namespace destruct

[chuck]

Summary

The driver calls nvme_ns_destruct for each possible namespace, not only
those which exist. The device alias code did not account for this and
will segfault.

Fix is to move destroying the alias device inside the cdev check.

[chuck]

@mav beat me to the fix.

sys/dev/nvme/nvme_ns.c

static struct ef10_external_port_map_s {
          * SFN7xx4F (Pavia):
          *      port 0 -> cage 1
          *      port 1 -> cage 2
          *      port 2 -> cage 3
          *      port 3 -> cage 4
          */
         {
                 EFX_FAMILY_HUNTINGTON,
-                (1 << TLV_PORT_MODE_10G) |
-                (1 << TLV_PORT_MODE_10G_10G) |
-                (1 << TLV_PORT_MODE_10G_10G_10G_10G),
-                1,
-                1
+                (1U << TLV_PORT_MODE_10G) |                        /* mode 0 */
+                (1U << TLV_PORT_MODE_10G_10G) |                        /* mode 2 */
+                (1U << TLV_PORT_MODE_10G_10G_10G_10G),                /* mode 4 */
+                1,        /* ports per cage */
+                1       /* first cage */
         },
         /*
          * Modes that on Medford allocate each port number to a separate
          * cage.
          *      port 0 -> cage 1
          *      port 1 -> cage 2
          *      port 2 -> cage 3
          *      port 3 -> cage 4
          */
         {
                 EFX_FAMILY_MEDFORD,
-                (1 << TLV_PORT_MODE_10G) |
-                (1 << TLV_PORT_MODE_10G_10G),
-                1,
-                1
+                (1U << TLV_PORT_MODE_10G) |                        /* mode 0 */
+                (1U << TLV_PORT_MODE_10G_10G),                        /* mode 2 */
+                1,        /* ports per cage */
+                1       /* first cage */
         },
         /*
          * Modes which for Huntington identify a chip variant where 2
          * adjacent port numbers map to each cage.
          * SFN7x42Q (Monza):
          *      port 0 -> cage 1
          *      port 1 -> cage 1
          *      port 2 -> cage 2
          *      port 3 -> cage 2
          */
         {
                 EFX_FAMILY_HUNTINGTON,
-                (1 << TLV_PORT_MODE_40G) |
-                (1 << TLV_PORT_MODE_40G_40G) |
-                (1 << TLV_PORT_MODE_40G_10G_10G) |
-                (1 << TLV_PORT_MODE_10G_10G_40G),
-                2,
-                1
+                (1U << TLV_PORT_MODE_40G) |                        /* mode 1 */
+                (1U << TLV_PORT_MODE_40G_40G) |                        /* mode 3 */
+                (1U << TLV_PORT_MODE_40G_10G_10G) |                /* mode 6 */
+                (1U << TLV_PORT_MODE_10G_10G_40G),                /* mode 7 */
+                2,        /* ports per cage */
+                1       /* first cage */
         },
         /*
          * Modes that on Medford allocate 2 adjacent port numbers to each
          * cage.
          *      port 0 -> cage 1
          *      port 1 -> cage 1
          *      port 2 -> cage 2
          *      port 3 -> cage 2
          */
         {
                 EFX_FAMILY_MEDFORD,
-                (1 << TLV_PORT_MODE_40G) |
-                (1 << TLV_PORT_MODE_40G_40G) |
-                (1 << TLV_PORT_MODE_40G_10G_10G) |
-                (1 << TLV_PORT_MODE_10G_10G_40G) |
-                (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),
-                2,
-                1
+                (1U << TLV_PORT_MODE_40G) |                        /* mode 1 */
+                (1U << TLV_PORT_MODE_40G_40G) |                        /* mode 3 */
+                (1U << TLV_PORT_MODE_40G_10G_10G) |                /* mode 6 */
+                (1U << TLV_PORT_MODE_10G_10G_40G) |                /* mode 7 */
+                /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
+                (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),        /* mode 9 */
+                2,        /* ports per cage */
+                1       /* first cage */
         },
         /*
          * Modes that on Medford allocate 4 adjacent port numbers to each
          * connector, starting on cage 1.
          *      port 0 -> cage 1
          *      port 1 -> cage 1
          *      port 2 -> cage 1
          *      port 3 -> cage 1
          */
         {
                 EFX_FAMILY_MEDFORD,
-                (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
-                (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),
-                4,
-                1,
+                (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q) |        /* mode 5 */
+                /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
+                (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1),        /* mode 4 */
+                4,        /* ports per cage */
+                1       /* first cage */
         },
         /*
          * Modes that on Medford allocate 4 adjacent port numbers to each
          * connector, starting on cage 2.
          *      port 0 -> cage 2
          *      port 1 -> cage 2
          *      port 2 -> cage 2
          *      port 3 -> cage 2
          */
         {
                 EFX_FAMILY_MEDFORD,
-                (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
-                4,
-                2
+                (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q2),        /* mode 8 */
+                4,        /* ports per cage */
+                2       /* first cage */
         },
 };
 
 static  __checkReturn   efx_rc_t
 ef10_external_port_mapping(
         __in            efx_nic_t *enp,
         __in            uint32_t port,
         __out           uint8_t *external_portp)