riscv: fix L0 PTE setup (Sv48)
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Authored by mhorne on May 15 2024, 3:48 PM.

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Reviewers

markj
jrtc27

Group Reviewers

riscv

Commits

rGed10a9398d05: riscv: fix L0 PTE setup (Sv48)
rGd7adf3b47a05: riscv: fix L0 PTE setup (Sv48)

Summary

Per the Privilege Spec, the Accessed (A) or Dirty (D) bits must only be
set for a leaf PTE.

It seems newer versions of QEMU have started to enforce this
requirement, and without this change, pmap_bootstrap() hangs when
switching to Sv48 mode.

Diff Detail

Repository

rG FreeBSD src repository

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Lint Passed

Unit

No Test Coverage

Build Status

Buildable 57715
Build 54603: arc lint + arc unit

Event Timeline

mhorne created this revision.May 15 2024, 3:48 PM

Herald added a subscriber: imp. · View Herald TranscriptMay 15 2024, 3:48 PM

mhorne requested review of this revision.May 15 2024, 3:48 PM

Harbormaster completed remote builds in B57715: Diff 138575.May 15 2024, 3:48 PM

jrtc27 accepted this revision.May 15 2024, 3:52 PM

This revision is now accepted and ready to land.May 15 2024, 3:52 PM

markj accepted this revision.May 15 2024, 3:55 PM

Closed by commit rGd7adf3b47a05: riscv: fix L0 PTE setup (Sv48) (authored by mhorne). · Explain WhyMay 15 2024, 5:09 PM

This revision was automatically updated to reflect the committed changes.

mhorne added a commit: rGd7adf3b47a05: riscv: fix L0 PTE setup (Sv48).

mhorne added a commit: rGed10a9398d05: riscv: fix L0 PTE setup (Sv48).May 27 2024, 2:44 PM

Revision Contents
Changeset List

Path

Size

sys/

riscv/

pmap.c

2 lines

Diff 138575

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riscv: fix L0 PTE setup (Sv48)ClosedPublicActions