arm64/disassem.c: Add detection of xzr and sp

[koliagogsadze_gmail.com]

Summary

Added support to distinguish between XZR/WZR and SP/WSP.
registers. Also "wSP" and "SP" were removed from w_reg and x_reg, since
num 31 can be SP or XZR, so a helper functions were introduced for this purpose
in arm64_reg to detect correct x31 register and added special
flags to determine if the instruction should be sp or xzr.

Test Plan

tested in the branch arm64-xzr-sp-support-tests:
https://github.com/toor1245/freebsd-src/pull/1/files
https://github.com/toor1245/freebsd-src/blob/arm64-xzr-sp-support-tests/sys/arm64/arm64/disassem.c

[koliagogsadze_gmail.com]

<Xn> or <Wn> are used to indicate case, where x31 refers to XZR.
<Xn|SP> or <Wn|WSP> are used to refer to a register, where x31 refers to the SP.

STR immediate example:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/STR--immediate---Store-Register--immediate--?lang=en

<Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Xt> Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

STR <Xt>, [<Xn|SP>, #<simm>]!

Here, we can use <Xn|SP> as x0-x30 or sp, and <Xt> as x0-x30 or xzr in others cases we will get expected compile error:

main.S:5:11: error: invalid operand for instruction
 str x0, [xzr, #8]!
           ^

Refs to review:

ADD:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ADD--shifted-register---Add--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/MOV--to-from-SP---Move-between-register-and-stack-pointer--an-alias-of-ADD--immediate--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ADD--immediate---Add--immediate--?lang=en

LDR:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDR--immediate---Load-Register--immediate--?lang=en
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDR--literal---Load-Register--literal--?lang=en
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en

LDRB:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRB--immediate---Load-Register-Byte--immediate--?lang=en
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRB--register---Load-Register-Byte--register--?lang=en

LDRH:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRH--immediate---Load-Register-Halfword--immediate--?lang=en
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRH--register---Load-Register-Halfword--register--?lang=en

LDRSB:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRSB--register---Load-Register-Signed-Byte--register--?lang=en
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRSB--immediate---Load-Register-Signed-Byte--immediate--?lang=en

LDRSH:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRSH--immediate---Load-Register-Signed-Halfword--immediate--?lang=en
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRSH--register---Load-Register-Signed-Halfword--register--?lang=en

LDRSW:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRSW--immediate---Load-Register-Signed-Word--immediate--?lang=en
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRSW--literal---Load-Register-Signed-Word--literal--?lang=en
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRSW--register---Load-Register-Signed-Word--register--?lang=en

STR:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/STR--immediate---Store-Register--immediate--?lang=en
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/STR--register---Store-Register--register--?lang=en

STRB:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/STRB--immediate---Store-Register-Byte--immediate--?lang=en
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/STRB--register---Store-Register-Byte--register--?lang=en

STRH:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/STRH--immediate---Store-Register-Halfword--immediate--?lang=en
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/STRH--register---Store-Register-Halfword--register--?lang=en

[mhorne]

sys/arm64/arm64/disassem.c

52–55

The majority of existing instruction definitions end up needing one or more of these flags. It seems like it would be better to flip the sense? In other words assume SP by default and define OP_RD_XZR instead.

367–382

I think these two can just be expanded inline, see my comment below.

383–389

This is how I would write the function. I see no reason to write 31 in binary.

[koliagogsadze_gmail.com]

sys/arm64/arm64/disassem.c

52–55

In general, XZR and SP are used together in almost every instruction.
For example:

LDRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]

https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRB--register---Load-Register-Byte--register--?lang=en

if we change LDRB (register) to SP by default from:

{ "ldrb", "00|111000010|IMM(9)|OPTION(2)|RN(5)|RT(5)",
    TYPE_02, OP_SIGN_EXT | OP_SF32 | OP_RN_SP }

it will look like this:

{ "ldrb", "00|111000010|IMM(9)|OPTION(2)|RN(5)|RT(5)",
    TYPE_02, OP_SIGN_EXT | OP_SF32 | OP_RT_XZR | OP_RM_XZR }

In other cases, nothing will change and we have to specify the flag, for example:

LDRH <Wt>, [<Xn|SP>], #<simm>

https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDRH--immediate---Load-Register-Halfword--immediate--?lang=en

I chose the default XZR as the lesser evil, since XZR occurs more frequently in an instruction definition more than once.

383–389

will update, thanks!

[koliagogsadze_gmail.com]

Inlined x31 detection functions

[mhorne]

LGTM

sys/arm64/arm64/disassem.c

52–55

Ahh understood, I agree with your assessment.