Cadence GEM core is used in various ARM, ARM64 and RISCV systems. There are some errata/quirks in different implementations, presented patch changes logic to enable them. As PolarFire SoC needs SGMII to connect PHY, 'phy-mode' property of device tree node for ethernet is checked and acted on appropriately. Also, fix a typo in if_cgem_hw.h file.
Build a kernel/module and test on available devices (Zynq based Zybo Z7 and Cora Z7 boards, PolarFire SoC based PF-RCHD SoM+carrier board from Conclusive Engineering) - it should be no change for all but PolarFire SoC based boards/devices.
Hi, thanks for the submission.
The quirk handling changes seem like a good improvement to me, but maybe @skibo has more of an opinion. They should be committed separately from the phy_contype + typo changes.
What device tree provides this compatible? I do not see it in the upstreamed bits for the PolarFire/MPFS Icicle Kit.
FYI, it is preferred (but not enforced) style within FreeBSD to be explicit like this for flag checks. You can see it elsewhere in this file.
...be moved down here? So that it is not in the middle of checking the quirks.
The problem with this is that HWQUIRK_NONE is zero which also means no match in the probe routine. Any board that uses the last three generic compatible strings won't match. How about HWQUIRK_NONE be 1 and move the other bits left.
No problem with this, I just think it could speed up the process a bit to discuss those together...
It is used in device tree presented from U-Boot as used in PF-RCHD SoM V1.0 - this is not published anywhere I think. I saw some compatible changes in MicroChip device trees, anyway, so it may change in future, too, but now it is this way. It would be great if someone with Icicle Kit could check, but I know no one who has it.
OK. Wait a moment, please, for new revision...
Definitelly, yes. In some older version it was not that visible. Here it is clearly better the way you show.