We actually do not know is it safe or not to flush cache for random BAR/register page existing in the system. It is well-known that for instance LAPICs cannot tolerate cache flush. As report indicates, there are more such devices. This issue typically affects AMD machines which do not report self-snoop, causing real CLFLUSH invocation on the mapped pages. Intels do self-snoop, so this change should be nop for them, and unsafe devices, if any, are already ignored.
apic: initialize lapic_paddr statically The default value for LAPIC registers page physical address is usually right. Having this value available early makes pmap_force_invalidate_cache_range(), used on non-self-snoop machines, avoid flushing LAPIC range for early calls.