Where does the bias of 2 come from?
From the clock schematic in the fu740 manual, pcieauxclk is not the child of hfpclk, but rather hfclk. I think the distinction would matter if we ever allow setting the pll clock frequency.
A lot of blank lines here... maybe lose this one?
So, is the generic clk_div class insufficient somehow?
Short answer: I used the Linux driver to infer the meaning of the register, as the manual is rather lacking in detail (though at least it documents this register unlike some of the others which are undocumented yet referred to by the Linux driver...)
The more elaborate answer is you can sort of infer this from the diagram. clktxclk is 0-250MHz and pclk is 0-125MHz, with pclk being clktxclk/N (ignoring buffers). Given the reset value of hfpclk_div is 0, that implies that 0 must mean 2 (as 250/125), and thus all values have an implicit +2 when used.
That's a good point, I suspect I just copied this from the divisor clock and failed to notice the subtle difference. Are we fine to assume the name of the clock in the device tree here, or do we need to make it dynamic?..
This was to mirror the style in prci_clk_pll_recalc, which I quite like as it separates out the MMIO from the normal calculation from the locking.
By default the real divisor is used, and you can also set a flag to have it start from 0, but there's no option to have a bias other than 0/1.