ccp: add new PCI ID for Zen 2/3

[val_packett.cool]

Summary

This is still CCP v5a; the PSP part (used for encrypted virtual machines etc) is different on that device, but we do not support that part.

ref: https://github.com/torvalds/linux/commit/dcbc0c6e4aa1ef269179351ac615fd08ddefc849

ccp0@pci0:12:0:1:       class=0x108000 rev=0x00 hdr=0x00 vendor=0x1022 device=0x1486 subvendor=0x1043 subdevice=0x8808
    vendor     = 'Advanced Micro Devices, Inc. [AMD]'
    device     = 'Starship/Matisse Cryptographic Coprocessor PSPCPP'
    class      = encrypt/decrypt

[cem]

See d7b665dfd7a6 / rS368542 / 7cda7375e629 / rS366943.

Also, ccp(4) is not really supported (known broken) and doesn't serve any purpose. Anything you could use ccp(4) for is better served by using aesni(4)/ossl(4) or RDRAND instead.

[val_packett.cool]

or RDRAND

Well, wouldn't mixing an extra source be better?

[cem]

In D27943#624066, @greg_unrelenting.technology wrote:

Well, wouldn't mixing an extra source be better?

I don't believe it's an independent source — I think RDSEED gets its outputs from the same source.

See: https://www.amd.com/system/files/TechDocs/amd-random-number-generator.pdf

Software Visibility
The RNG includes 3 read-only output registers which provide visibility at different parts of the RNG flow. These registers are accessible through the AMD Secure Processor MMIO space for x86 software, and in some cases are also available through x86 user-level instructions:

MMIO register	...	Equivalent x86 instruction
TRNG_OUT	...	RDRAND
TRNG_SEED	...	RDSEED

An earlier version of the same document (56310 "AMD Secure Random Number Generator Library") said, explicitly:

Every time you invoke the RDRAND or RDSEED instruction it reads a value from the cryptographic co-processor block.