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Limit workaround for errata E400 to appropriate AMD cpus.
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Authored by kib on Sep 17 2020, 6:37 PM.

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Summary

From Linux sources and different datasheets I looked at, it seems that the workaround is only needed on families 0xf and 0x10. For instance, Ryzens do not implement the accessed MSR, it is documented as reserved. Also, hypervisors should not allow guest to put CPU into idle state, so activate workaround only when on bare hardware.

While there, style the code:

  • move MSR defines to specialreg.h
  • move identification to initcpu.c

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