UART has a register LSR, line status register. Every time there is a read on this register the error bits are cleared. The current implementation reads the LSR register to detect if data was received uart_core.c - uart_intr -> ns8250_bus_ipend and then reads data from the DATA register ns8250_bus_receive. Into the ns8250_bus_receive, LSR is read again to determine if there were any errors (parity, frame). At this point the error bit is cleared by the previews LSR read. As a result parity and frame errors are never detected. See  for more details.
The suggested solution is to add an extra member into the ns8250 structure to store the LSR value for later use, so that the byte that was read from the DATA register is in sync with the LSR register.