Invalidate cache for the pdir page when using PAE paging but PAT is not supported.

[kib]

Summary

According to SDM rev. 69 vol. 3, for PDPTE registers loads:

• when PAT is not supported, access to the pdir page is performed as UC, see 4.9.1;
• when PAT is supported, the access is WB, see 4.9.2.

So potentially CPU might load stale memory as PDPTEs if both PAT and self-snoop are not implemented. To be safe, add total local cache flush to pmap_cold() before initial load of cr3, and flush pdir in pmap_pinit(), if PAT is not implemented.

PS. Due to a note in 4.9.2 I was tempted to always flush pdir, but then backed it off.

[markj]

PS. Due to a note in 4.9.2 I was tempted to always flush pdir, but then backed it off.

Because the note implicitly applies only when PAT is supported?

sys/i386/i386/pmap.c

2048 ↗

(On Diff #54411)

Shouldn't it be pm_pdir + NBPTD?

[kib]

In D19365#415454, @markj wrote:

PS. Due to a note in 4.9.2 I was tempted to always flush pdir, but then backed it off.

Because the note implicitly applies only when PAT is supported?

My initial interpretation was that it somehow applies to older processor but with PAT support.
My later interpretation of 'some older IA-32 processors' is 'processors that are older than PAT support', esp. in conjunction with reference to 4.9.1. After I backed it off, I consider that the note claims that some pre-PAT processors might use WB and not UB.

sys/i386/i386/pmap.c

2048 ↗

(On Diff #54411)

It should be (vm_offset_t)pmap->pm_pdir + NPGPTD * sizeof(pdpt_entry_t), but because pmap_invalidate_cache_range() asserts that start and end are on page boundary, I decided to be more explicit.

[markj]

sys/i386/i386/pmap.c

2048 ↗

(On Diff #54411)

Shouldn't it be flushing pmap->pm_pdpt then?

[kib]

Fix the location which is invalidated.