Add 0xb OR opcode support to bhyve's instruction emulation
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Authored by grehan on Oct 30 2017, 7:17 AM.

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araujo

imp

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Reviewers

araujo

Group Reviewers

bhyve

Commits

rS325261: Emulate the "OR reg, r/m" instruction (opcode 0BH).

Summary

The FreeBSD HDA code uses the 0xb variant of OR when accessing
device registers. Add this emulation, using the pattern of
existing OR code.

Test Plan

Run the HDA emulation patch with a FreeBSD 11.1 guest, and cat a .wav
file to /dev/dsp.

Diff Detail

Repository

rS FreeBSD src repository - subversion

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Lint Passed

Unit

No Test Coverage

Build Status

Buildable 12296
Build 12585: arc lint + arc unit

Event Timeline

grehan created this revision.Oct 30 2017, 7:17 AM

Herald added a subscriber: imp. · View Herald TranscriptOct 30 2017, 7:17 AM

Harbormaster completed remote builds in B12296: Diff 34447.Oct 30 2017, 7:17 AM

LGTM!

This revision is now accepted and ready to land.Oct 30 2017, 7:28 AM

Closed by commit rS325261: Emulate the "OR reg, r/m" instruction (opcode 0BH). (authored by grehan). · Explain WhyNov 1 2017, 3:27 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents
Changeset List

Path

Size

sys/

amd64/

vmm/

vmm_instruction_emul.c

32 lines

Diff 34447

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sys/amd64/vmm/vmm_instruction_emul.c

Add 0xb OR opcode support to bhyve's instruction emulationClosedPublicActions