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Enable HWPMC overflow IRQ on both CPUs in MPIC
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Authored by mw_semihalf.com on May 25 2017, 3:36 PM.

Details

Summary

This commit enables usage of HWPMC interrupts for the
Marvell SoCs, which use MPIC (Armada38x and ArmadaXP).
Those interrupts require extra unmasking, comparing to
others. Also, in order to process counters per-CPU,
they are masked/unmasked using separate registers' sets
for each core.

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Repository
rS FreeBSD src repository
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Unit
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This revision was automatically updated to reflect the committed changes.