Enable HWPMC overflow IRQ on both CPUs in MPIC

This commit enables usage of HWPMC interrupts for the
Marvell SoCs, which use MPIC (Armada38x and ArmadaXP).
Those interrupts require extra unmasking, comparing to
others. Also, in order to process counters per-CPU,
they are masked/unmasked using separate registers' sets
for each core.

Submitted by: Michal Mazur <mkm@semihalf.com>

	      Marcin Wojtas <mw@semihalf.com>

Obtained from: Semihalf
Sponsored by: Stormshield, Netgate
Differential revision: https://reviews.freebsd.org/D10913