Diffusion FreeBSD src repository - subversion rS339367

Various fixes for TLB management on RISC-V.
rS339367
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Description

Various fixes for TLB management on RISC-V.

Remove the arm64-specific cpu_*cache* and cpu_tlb_flush* functions. Instead, add RISC-V specific inline functions in cpufunc.h for the fence.i and sfence.vma instructions.
Catch up to changes in the arm64 pmap and remove all the cpu_dcache_* calls, pmap_is_current, pmap_l3_valid_cacheable, and PTE_NEXT bits from pmap.
Remove references to the unimplemented riscv_setttb().
Remove unused cpu_nullop.
Add a link to the SBI doc to sbi.h.
Add support for a 4th argument in SBI calls. It's not documented but it seems implied for the asid argument to SBI_REMOVE_SFENCE_VMA_ASID.
Pass the arguments from sbi_remote_sfence*() to the SEE. BBL ignores them so this is just cosmetic.
Flush icaches on other CPUs when they resume from kdb in case the debugger wrote any breakpoints while the CPUs were paused in the IPI_STOP handler.
Add SMP vs UP versions of pmap_invalidate_* similar to amd64. The UP versions just use simple fences. The SMP versions use the sbi_remove_sfence*() functions to perform TLB shootdowns. Since we don't have a valid pm_active field in the riscv pmap, just IPI all CPUs for all invalidations for now.
Remove an extraneous TLB flush from the end of pmap_bootstrap().
Don't do a TLB flush when writing new mappings in pmap_enter(), only if modifying an existing mapping. Note that for COW faults a TLB flush is only performed after explicitly clearing the old mapping as is done in other pmaps.
Sync the i-cache on all harts before updating the PTE for executable mappings in pmap_enter and pmap_enter_quick. Previously the i-cache was only sync'd after updating the PTE in pmap_enter.
Use sbi_remote_fence() instead of smp_rendezvous in pmap_sync_icache().