In D40006#912681, @mhorne wrote:

The wording used by the docs is confusing, but it is actually saying that disassemblers should output the aliases when possible.

For example, we should print cmn x2, #1 rather than adds xzr, x2, #1.

This is the behaviour of GNU and LLVM objdump utilities.

May 13 2023, 1:08 PM

koliagogsadze_gmail.com updated the summary of D40006: arm64/disassem.c: Add support insts of shifted register with rsv option.

May 13 2023, 6:08 AM

May 8 2023

koliagogsadze_gmail.com added a comment to D40006: arm64/disassem.c: Add support insts of shifted register with rsv option.

refs to review:
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/ADDS--shifted-register---Add--shifted-register---setting-flags-
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/CMN--shifted-register---Compare-Negative--shifted-register---an-alias-of-ADDS--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/CMP--shifted-register---Compare--shifted-register---an-alias-of-SUBS--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/NEG--shifted-register---Negate--shifted-register---an-alias-of-SUB--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/NEGS--Negate--setting-flags--an-alias-of-SUBS--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/SUB--shifted-register---Subtract--shifted-register--
https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/SUBS--shifted-register---Subtract--shifted-register---setting-flags-

May 8 2023, 8:06 PM

koliagogsadze_gmail.com requested review of D40006: arm64/disassem.c: Add support insts of shifted register with rsv option.

May 8 2023, 7:58 PM

koliagogsadze_gmail.com abandoned D40005: arm64/disassem.c: Add support insts of shifted register with rsv option.

May 8 2023, 7:56 PM

koliagogsadze_gmail.com requested review of D40005: arm64/disassem.c: Add support insts of shifted register with rsv option.

May 8 2023, 7:55 PM

koliagogsadze_gmail.com updated the diff for D39820: arm64/disassem.c: make output in lowercase register to consistency.

Rebased with main branch

May 8 2023, 5:24 PM

Apr 29 2023

koliagogsadze_gmail.com updated the diff for D39862: arm64/disassem.c: Add detection of xzr and sp.

Inlined x31 detection functions

Apr 29 2023, 9:12 PM

koliagogsadze_gmail.com added inline comments to D39862: arm64/disassem.c: Add detection of xzr and sp.

Apr 29 2023, 5:17 PM

Apr 27 2023

koliagogsadze_gmail.com added a comment to D39862: arm64/disassem.c: Add detection of xzr and sp.

<Xn> or <Wn> are used to indicate case, where x31 refers to XZR.
<Xn|SP> or <Wn|WSP> are used to refer to a register, where x31 refers to the SP.

Apr 27 2023, 11:39 PM

koliagogsadze_gmail.com abandoned D39861: arm64/disassem.c: Add detection of xzr and sp.

Apr 27 2023, 10:50 PM

koliagogsadze_gmail.com requested review of D39862: arm64/disassem.c: Add detection of xzr and sp.

Apr 27 2023, 10:48 PM

koliagogsadze_gmail.com requested review of D39861: arm64/disassem.c: Add detection of xzr and sp.

Apr 27 2023, 10:44 PM

Apr 25 2023

koliagogsadze_gmail.com updated the diff for D39820: arm64/disassem.c: make output in lowercase register to consistency.

Apr 25 2023, 10:27 PM

koliagogsadze_gmail.com requested review of D39820: arm64/disassem.c: make output in lowercase register to consistency.

Apr 25 2023, 10:06 PM

Apr 24 2023

koliagogsadze_gmail.com added a comment to D39334: arm64/disassem.c: Fix typo sxts to sxts and amount for TYPE_02.

In D39334#905622, @mhorne wrote:
Hi, sorry for the delay. I was looking at the change again before merging, and now it doesn't seem quite right to me.

https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en#sa_amount_1

It seems like in this code we will only ever set amount to 1 or 0. But in the link above it seems like the only legal values are: #0, #2, and #3, depending on the <size> parameter of the instruction.

Should it be something like this?
if (scale == 0)
    amount = 0;
else {
    if (((insn >> ARM_INSN_SIZE_OFFSET) & ARM_INSN_SIZE_MASK) != 0)
        /* <size> == 64-bit */
        amount = 3;
    else
        /* <size> == 32-bit */
        amount = 2;
}