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	#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */	#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */
	#define EXCP_BRK 0x3c /* Breakpoint */	#define EXCP_BRK 0x3c /* Breakpoint */

		/* ICC_CTLR_EL1 */
		#define ICC_CTLR_EL1_EOIMODE (1U << 1)

		/* ICC_IAR1_EL1 */
		#define ICC_IAR1_EL1_SPUR (0x03ff)

		/* ICC_IGRPEN0_EL1 */
		#define ICC_IGRPEN0_EL1_EN (1U << 0)
		andrewUnsubmitted Done Inline Actions This should be `ICC_CTLR_EL1_EOIMODE` andrew: This should be `ICC_CTLR_EL1_EOIMODE`

		/* ICC_PMR_EL1 */
		#define ICC_PMR_EL1_PRIO_MASK (0xFFUL)

		/* ICC_SRE_EL1 */
		#define ICC_SRE_EL1_SRE (1U << 0)
		andrewUnsubmitted Done Inline Actions I don't see this in the ARMv8 ARM, is it documented differently in the GICv3 docs? andrew: I don't see this in the ARMv8 ARM, is it documented differently in the GICv3 docs?
		zbbAuthorUnsubmitted Done Inline Actions To avoid another ping-pong: 1023 is a spurious interrupt ID that is described in GICv3 docs and is being read from ICC_IAR1_EL1 register. Do you ask because: you want it moved/redefined somewhere else? for other reason (explain) zbb: To avoid another ping-pong: 1023 is a spurious interrupt ID that is described in GICv3 docs and…
		andrewUnsubmitted Done Inline Actions Ok, this is one of the problems with me not having GICv3 docs,I'm unsure what is in there that may be useful. andrew: Ok, this is one of the problems with me not having GICv3 docs,I'm unsure what is in there that…

		andrewUnsubmitted Done Inline Actions In general I've tried to add all the used bits when adding new register values, and the registers should be alphabetically sorted by name. andrew: In general I've tried to add all the used bits when adding new register values, and the…
		ianUnsubmitted Done Inline Actions Eeek! No way -- the registers should be sorted ascending by address, not by name, so that they match the way they're documented. (I've yet to see a soc manual arrange register docs alphabetical as opposed to by address.) ian: Eeek! No way -- the registers should be sorted ascending by address, not by name, so that they…
		andrewUnsubmitted Done Inline Actions These are special registers, they are listed by name in the docs. There is sort of an address (as much of one as the 32-bit coprocessor registers), but only the assembler needs to know about it. andrew: These are special registers, they are listed by name in the docs. There is sort of an address…
		/* ICC_SRE_EL2 */
		#define ICC_SRE_EL2_EN (1U << 3)

	/* ID_AA64PFR0_EL1 */	/* ID_AA64PFR0_EL1 */
	#define ID_AA64PFR0_EL0_MASK (0xf << 0)	#define ID_AA64PFR0_EL0_MASK (0xf << 0)
	#define ID_AA64PFR0_EL1_MASK (0xf << 4)	#define ID_AA64PFR0_EL1_MASK (0xf << 4)
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	#define ID_AA64PFR0_FP_IMPL (0x0 << 16) /* Floating-point implemented */	#define ID_AA64PFR0_FP_IMPL (0x0 << 16) /* Floating-point implemented */
	#define ID_AA64PFR0_FP_NONE (0xf << 16) /* Floating-point not implemented */	#define ID_AA64PFR0_FP_NONE (0xf << 16) /* Floating-point not implemented */
	#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << 20)	#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << 20)
	#define ID_AA64PFR0_GIC_MASK (0xf << 24)	#define ID_AA64PFR0_GIC_SHIFT (24)
		#define ID_AA64PFR0_GIC_BITS (0x4) /* Number of bits in GIC field */
		#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT)
		#define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT)

	/* MAIR_EL1 - Memory Attribute Indirection Register */	/* MAIR_EL1 - Memory Attribute Indirection Register */
	#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))	#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
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libpfctl: fix double free
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