The Zynq SLCR block assumes the Ethernet refernence clock is always sourced
from the IO_PLL. But, to put an Ethernet PHY design in the PL (FPGA) often
requires the reference clock to come from the PL instead. This fix allows
the Ethernet clock to come from any PLL as well as from the PL (via EMIO).
In the case of EMIO sourced clock, the clock dividers are ignored and it
is assumed the PL adjusts the clock frequency when the media changes.

I don't have access to a design with Ethernet connected to the PL. But, I
have tested that the change doesn't affect the more common case of
Ethernet connected to the PS.