While cause codes higher than 16 are reserved, the exception code field
of the register is defined to be all bits but the upper most bit.
Details
Details
- Reviewers
mhorne br - Commits
- rS357595: Fix EXCP_MASK to include all relevant bits from scause.
- CHERI RISC-V uses exception code 0x1c which was truncated to 0xc with the current mask
Diff Detail
Diff Detail
- Lint
Lint Skipped - Unit
Tests Skipped - Build Status
Buildable 29174 Build 27106: arc lint + arc unit