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Differential D22474

Add option to run rpc.{lockd,statd} in the foreground.
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Authored by rpokala on Nov 21 2019, 5:21 AM.
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rS355006: Add and document options to allow rpc.lockd and rpc.statd to run in the
Summary

Add and document options to allow rpc.lockd and rpc.statd to run in the
foreground.

This allows a separate process to monitor when and how those programs exit.
That process can then restart them if needed.

Diff Detail

Repository
rS FreeBSD src repository - subversion
Lint
Lint Passed
Unit
No Test Coverage
Build Status
Buildable 27717
Build 25916: arc lint + arc unit

Event Timeline

rpokala created this revision.Nov 21 2019, 5:21 AM
Herald added a reviewer: manpages. · View Herald TranscriptNov 21 2019, 5:21 AM
Herald added a subscriber: imp. · View Herald Transcript
Harbormaster completed remote builds in B27675: Diff 64663.Nov 21 2019, 5:21 AM
imp accepted this revision.Nov 21 2019, 11:28 PM

Looks good to me. Other commands use different flags to run in foreground, though. IT's inconsistent...

This revision is now accepted and ready to land.Nov 21 2019, 11:28 PM
rpokala added a comment.Nov 22 2019, 12:19 AM
In D22474#491849, @imp wrote:

Looks good to me. Other commands use different flags to run in foreground, though. IT's inconsistent...

Yeah, I've noticed. :-/

rpokala updated this revision to Diff 64731.Nov 22 2019, 4:38 PM

Split lines in the manpages at the start of new sentences. Thanks igor(1)!

This revision now requires review to proceed.Nov 22 2019, 4:38 PM
Harbormaster completed remote builds in B27717: Diff 64731.Nov 22 2019, 4:38 PM
bcr accepted this revision.Nov 22 2019, 4:51 PM
bcr added a subscriber: bcr.
In D22474#492077, @rpokala wrote:

Split lines in the manpages at the start of new sentences. Thanks igor(1)!

Isn't it a nice lab assistant? ;)
BTW, approved by manpages!

This revision is now accepted and ready to land.Nov 22 2019, 4:51 PM
Closed by commit rS355006: Add and document options to allow rpc.lockd and rpc.statd to run in the (authored by rpokala). · Explain WhyNov 22 2019, 4:53 PM
This revision was automatically updated to reflect the committed changes.
rpokala added a commit: rS355006: Add and document options to allow rpc.lockd and rpc.statd to run in the.

Revision Contents
Changeset List

PathSize
usr.sbin/
rpc.lockd/
10 lines
14 lines
rpc.statd/
14 lines
14 lines

Diff 64731

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usr.sbin/rpc.lockd/lockd.c

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
#define PCIE_REG_MASK 0xFFF #define PCIE_REG_MASK 0xFFF
#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
(((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
((reg) & PCIE_REG_MASK)) ((reg) & PCIE_REG_MASK))
typedef void (*pci_host_generic_quirk_function)(device_t);
struct pci_host_generic_quirk_entry {
int impl;
int part;
int var;
int rev;
pci_host_generic_quirk_function func;
};
struct pci_host_generic_block_entry {
int impl;
int part;
int var;
int rev;
int bus;
int slot;
};
/* Forward prototypes */ /* Forward prototypes */
static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes); u_int func, u_int reg, int bytes);
static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, uint32_t val, int bytes); u_int func, u_int reg, uint32_t val, int bytes);
static int generic_pcie_maxslots(device_t dev); static int generic_pcie_maxslots(device_t dev);
static int generic_pcie_read_ivar(device_t dev, device_t child, int index, static int generic_pcie_read_ivar(device_t dev, device_t child, int index,
uintptr_t *result); uintptr_t *result);
static int generic_pcie_write_ivar(device_t dev, device_t child, int index, static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
uintptr_t value); uintptr_t value);
static void pci_host_generic_apply_quirks(device_t);
static void thunderx2_ahci_bar_quirk(device_t);
struct pci_host_generic_quirk_entry pci_host_generic_quirks[] =
{
{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, thunderx2_ahci_bar_quirk},
{0, 0, 0, 0, NULL}
};
struct pci_host_generic_block_entry pci_host_generic_blocked[] =
{
/* ThunderX2 AHCI on second socket */
{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, 0x80, 0x10},
{0, 0, 0, 0, 0, 0}
};
andrewUnsubmitted
Not Done
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Why is this needed?

andrew: Why is this needed?
pdk_semihalf.comAuthorUnsubmitted
Not Done
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Second socket have SATA controller on chip. It is not exposed on board, and have bad adresses (like SATA on first socket). Instead of fixing addresses we block it.

pdk_semihalf.com: Second socket have SATA controller on chip. It is not exposed on board, and have bad adresses…
int int
pci_host_generic_core_attach(device_t dev) pci_host_generic_core_attach(device_t dev)
{ {
struct generic_pcie_core_softc *sc; struct generic_pcie_core_softc *sc;
int error; int error;
int rid; int rid;
sc = device_get_softc(dev); sc = device_get_softc(dev);
Show All 37 Linespci_host_generic_core_attach(device_t dev)
} }
error = rman_init(&sc->io_rman); error = rman_init(&sc->io_rman);
if (error) { if (error) {
device_printf(dev, "rman_init() failed. error = %d\n", error); device_printf(dev, "rman_init() failed. error = %d\n", error);
return (error); return (error);
} }
pci_host_generic_apply_quirks(dev);
return (0); return (0);
} }
static void
pci_host_generic_apply_quirks(device_t dev)
{
struct pci_host_generic_quirk_entry *quirk;
quirk = pci_host_generic_quirks;
while (1) {
if (quirk->impl == 0)
break;
if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
quirk->impl, quirk->part, quirk->var, quirk->rev) &&
quirk->func != NULL)
quirk->func(dev);
quirk++;
}
}
static uint32_t static uint32_t
generic_pcie_read_config(device_t dev, u_int bus, u_int slot, generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes) u_int func, u_int reg, int bytes)
{ {
struct generic_pcie_core_softc *sc; struct generic_pcie_core_softc *sc;
bus_space_handle_t h; bus_space_handle_t h;
bus_space_tag_t t; bus_space_tag_t t;
uint64_t offset; uint64_t offset;
uint32_t data; uint32_t data;
struct pci_host_generic_block_entry *block;
if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
return (~0U); return (~0U);
block = pci_host_generic_blocked;
while (1) {
if (block->impl == 0)
break;
if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
block->impl, block->part, block->var, block->rev) &&
block->bus == bus && block->slot == slot)
return (~0);
block++;
}
sc = device_get_softc(dev); sc = device_get_softc(dev);
offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
t = sc->bst; t = sc->bst;
h = sc->bsh; h = sc->bsh;
switch (bytes) { switch (bytes) {
case 1: case 1:
▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Linesstatic device_method_t generic_pcie_methods[] = {
DEVMETHOD(pcib_read_config, generic_pcie_read_config), DEVMETHOD(pcib_read_config, generic_pcie_read_config),
DEVMETHOD(pcib_write_config, generic_pcie_write_config), DEVMETHOD(pcib_write_config, generic_pcie_write_config),
DEVMETHOD_END DEVMETHOD_END
}; };
DEFINE_CLASS_0(pcib, generic_pcie_core_driver, DEFINE_CLASS_0(pcib, generic_pcie_core_driver,
generic_pcie_methods, sizeof(struct generic_pcie_core_softc)); generic_pcie_methods, sizeof(struct generic_pcie_core_softc));
static void thunderx2_ahci_bar_quirk(device_t dev)
{
/*
* XXX:
* On ThunderX2, AHCI BAR2 address is wrong. It needs to precisely
* match the one described in datasheet. Fixup it unconditionally.
andrewUnsubmitted
Not Done
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Is there an erratum for this?

andrew: Is there an erratum for this?
pdk_semihalf.comAuthorUnsubmitted
Not Done
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There is no erratum. Without this quirk kernel is trying to access bad address.

pdk_semihalf.com: There is no erratum. Without this quirk kernel is trying to access bad address.
andrewUnsubmitted
Not Done
Inline Actions

Why is the kernel trying to access a bad address?

andrew: Why is the kernel trying to access a bad address?
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

Kernel is trying to attach ahci. Look at log (without quirk of course) below it contains aforementioned bad address:

ahci0: <AHCI SATA controller> mem 0x41d4100041d30000-0x41d4100041d3ffff,0x41d20000-0x41d2ffff at device 16.0 on pci0                
PDK: virtual=0xffff000165388000 size=65536 pa=41d20000                                                                              
PDK: virtual=0xffff000165398000 size=65536 pa=41d4100041d30000                                                                      
ahci0: PDK: msix_table_bar: 24                                                                                                      
ahci0: PDK: msix_table_res: 0xfffffd0001e25180                                                                                      
ahci0: attempting to allocate 4 MSI-X vectors (4 supported)                                                                         
ahci0: using IRQs 11-14 for MSI-X                                                                                                                                                                                                                                                                                               
panic: vm_fault_hold: fault on nofault entry, addr: 0xffff000165398000
pdk_semihalf.com: Kernel is trying to attach ahci. Look at log (without quirk of course) below it contains…
*/
if (device_get_unit(dev) == 0) {
device_printf(dev, "running AHCI BAR fixup\n");
PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x18, 0x01440000, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x1c, 0x40, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x18, 0x01450000, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x1c, 0x40, 4);
}
}
andrewUnsubmitted
Not Done
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Shouldn't you be getting this from the ACPI mcfg table?

andrew: Shouldn't you be getting this from the ACPI mcfg table?
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

Yes, I should get this from MCFG, but it doesn't provide information about pci on second socket. Furthermore segment passed to acpi_enable_pcie is 0 in both cases.

pdk_semihalf.com: Yes, I should get this from MCFG, but it doesn't provide information about pci on second socket.
andrewUnsubmitted
Not Done
Inline Actions

Will this always be unit 16, or would it be better to look at other information to detect when it's an ecam device.

andrew: Will this always be unit 16, or would it be better to look at other information to detect when…
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

It will be always unit 16. I've checked it once again and I have an idea. I will use _BBN to get ecam number. I'll update patches today so stay tuned.

pdk_semihalf.com: It will be always unit 16. I've checked it once again and I have an idea. I will use _BBN to…
View Options

usr.sbin/rpc.lockd/rpc.lockd.8

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
#define PCIE_REG_MASK 0xFFF #define PCIE_REG_MASK 0xFFF
#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
(((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
((reg) & PCIE_REG_MASK)) ((reg) & PCIE_REG_MASK))
typedef void (*pci_host_generic_quirk_function)(device_t);
struct pci_host_generic_quirk_entry {
int impl;
int part;
int var;
int rev;
pci_host_generic_quirk_function func;
};
struct pci_host_generic_block_entry {
int impl;
int part;
int var;
int rev;
int bus;
int slot;
};
/* Forward prototypes */ /* Forward prototypes */
static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes); u_int func, u_int reg, int bytes);
static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, uint32_t val, int bytes); u_int func, u_int reg, uint32_t val, int bytes);
static int generic_pcie_maxslots(device_t dev); static int generic_pcie_maxslots(device_t dev);
static int generic_pcie_read_ivar(device_t dev, device_t child, int index, static int generic_pcie_read_ivar(device_t dev, device_t child, int index,
uintptr_t *result); uintptr_t *result);
static int generic_pcie_write_ivar(device_t dev, device_t child, int index, static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
uintptr_t value); uintptr_t value);
static void pci_host_generic_apply_quirks(device_t);
static void thunderx2_ahci_bar_quirk(device_t);
struct pci_host_generic_quirk_entry pci_host_generic_quirks[] =
{
{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, thunderx2_ahci_bar_quirk},
{0, 0, 0, 0, NULL}
};
struct pci_host_generic_block_entry pci_host_generic_blocked[] =
{
/* ThunderX2 AHCI on second socket */
{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, 0x80, 0x10},
{0, 0, 0, 0, 0, 0}
};
andrewUnsubmitted
Not Done
Inline Actions

Why is this needed?

andrew: Why is this needed?
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

Second socket have SATA controller on chip. It is not exposed on board, and have bad adresses (like SATA on first socket). Instead of fixing addresses we block it.

pdk_semihalf.com: Second socket have SATA controller on chip. It is not exposed on board, and have bad adresses…
int int
pci_host_generic_core_attach(device_t dev) pci_host_generic_core_attach(device_t dev)
{ {
struct generic_pcie_core_softc *sc; struct generic_pcie_core_softc *sc;
int error; int error;
int rid; int rid;
sc = device_get_softc(dev); sc = device_get_softc(dev);
Show All 37 Linespci_host_generic_core_attach(device_t dev)
} }
error = rman_init(&sc->io_rman); error = rman_init(&sc->io_rman);
if (error) { if (error) {
device_printf(dev, "rman_init() failed. error = %d\n", error); device_printf(dev, "rman_init() failed. error = %d\n", error);
return (error); return (error);
} }
pci_host_generic_apply_quirks(dev);
return (0); return (0);
} }
static void
pci_host_generic_apply_quirks(device_t dev)
{
struct pci_host_generic_quirk_entry *quirk;
quirk = pci_host_generic_quirks;
while (1) {
if (quirk->impl == 0)
break;
if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
quirk->impl, quirk->part, quirk->var, quirk->rev) &&
quirk->func != NULL)
quirk->func(dev);
quirk++;
}
}
static uint32_t static uint32_t
generic_pcie_read_config(device_t dev, u_int bus, u_int slot, generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes) u_int func, u_int reg, int bytes)
{ {
struct generic_pcie_core_softc *sc; struct generic_pcie_core_softc *sc;
bus_space_handle_t h; bus_space_handle_t h;
bus_space_tag_t t; bus_space_tag_t t;
uint64_t offset; uint64_t offset;
uint32_t data; uint32_t data;
struct pci_host_generic_block_entry *block;
if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
return (~0U); return (~0U);
block = pci_host_generic_blocked;
while (1) {
if (block->impl == 0)
break;
if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
block->impl, block->part, block->var, block->rev) &&
block->bus == bus && block->slot == slot)
return (~0);
block++;
}
sc = device_get_softc(dev); sc = device_get_softc(dev);
offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
t = sc->bst; t = sc->bst;
h = sc->bsh; h = sc->bsh;
switch (bytes) { switch (bytes) {
case 1: case 1:
▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Linesstatic device_method_t generic_pcie_methods[] = {
DEVMETHOD(pcib_read_config, generic_pcie_read_config), DEVMETHOD(pcib_read_config, generic_pcie_read_config),
DEVMETHOD(pcib_write_config, generic_pcie_write_config), DEVMETHOD(pcib_write_config, generic_pcie_write_config),
DEVMETHOD_END DEVMETHOD_END
}; };
DEFINE_CLASS_0(pcib, generic_pcie_core_driver, DEFINE_CLASS_0(pcib, generic_pcie_core_driver,
generic_pcie_methods, sizeof(struct generic_pcie_core_softc)); generic_pcie_methods, sizeof(struct generic_pcie_core_softc));
static void thunderx2_ahci_bar_quirk(device_t dev)
{
/*
* XXX:
* On ThunderX2, AHCI BAR2 address is wrong. It needs to precisely
* match the one described in datasheet. Fixup it unconditionally.
andrewUnsubmitted
Not Done
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Is there an erratum for this?

andrew: Is there an erratum for this?
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

There is no erratum. Without this quirk kernel is trying to access bad address.

pdk_semihalf.com: There is no erratum. Without this quirk kernel is trying to access bad address.
andrewUnsubmitted
Not Done
Inline Actions

Why is the kernel trying to access a bad address?

andrew: Why is the kernel trying to access a bad address?
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

Kernel is trying to attach ahci. Look at log (without quirk of course) below it contains aforementioned bad address:

ahci0: <AHCI SATA controller> mem 0x41d4100041d30000-0x41d4100041d3ffff,0x41d20000-0x41d2ffff at device 16.0 on pci0                
PDK: virtual=0xffff000165388000 size=65536 pa=41d20000                                                                              
PDK: virtual=0xffff000165398000 size=65536 pa=41d4100041d30000                                                                      
ahci0: PDK: msix_table_bar: 24                                                                                                      
ahci0: PDK: msix_table_res: 0xfffffd0001e25180                                                                                      
ahci0: attempting to allocate 4 MSI-X vectors (4 supported)                                                                         
ahci0: using IRQs 11-14 for MSI-X                                                                                                                                                                                                                                                                                               
panic: vm_fault_hold: fault on nofault entry, addr: 0xffff000165398000
pdk_semihalf.com: Kernel is trying to attach ahci. Look at log (without quirk of course) below it contains…
*/
if (device_get_unit(dev) == 0) {
device_printf(dev, "running AHCI BAR fixup\n");
PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x18, 0x01440000, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x1c, 0x40, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x18, 0x01450000, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x1c, 0x40, 4);
}
}
andrewUnsubmitted
Not Done
Inline Actions

Shouldn't you be getting this from the ACPI mcfg table?

andrew: Shouldn't you be getting this from the ACPI mcfg table?
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

Yes, I should get this from MCFG, but it doesn't provide information about pci on second socket. Furthermore segment passed to acpi_enable_pcie is 0 in both cases.

pdk_semihalf.com: Yes, I should get this from MCFG, but it doesn't provide information about pci on second socket.
andrewUnsubmitted
Not Done
Inline Actions

Will this always be unit 16, or would it be better to look at other information to detect when it's an ecam device.

andrew: Will this always be unit 16, or would it be better to look at other information to detect when…
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

It will be always unit 16. I've checked it once again and I have an idea. I will use _BBN to get ecam number. I'll update patches today so stay tuned.

pdk_semihalf.com: It will be always unit 16. I've checked it once again and I have an idea. I will use _BBN to…
View Options

usr.sbin/rpc.statd/rpc.statd.8

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
#define PCIE_REG_MASK 0xFFF #define PCIE_REG_MASK 0xFFF
#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
(((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
((reg) & PCIE_REG_MASK)) ((reg) & PCIE_REG_MASK))
typedef void (*pci_host_generic_quirk_function)(device_t);
struct pci_host_generic_quirk_entry {
int impl;
int part;
int var;
int rev;
pci_host_generic_quirk_function func;
};
struct pci_host_generic_block_entry {
int impl;
int part;
int var;
int rev;
int bus;
int slot;
};
/* Forward prototypes */ /* Forward prototypes */
static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes); u_int func, u_int reg, int bytes);
static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, uint32_t val, int bytes); u_int func, u_int reg, uint32_t val, int bytes);
static int generic_pcie_maxslots(device_t dev); static int generic_pcie_maxslots(device_t dev);
static int generic_pcie_read_ivar(device_t dev, device_t child, int index, static int generic_pcie_read_ivar(device_t dev, device_t child, int index,
uintptr_t *result); uintptr_t *result);
static int generic_pcie_write_ivar(device_t dev, device_t child, int index, static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
uintptr_t value); uintptr_t value);
static void pci_host_generic_apply_quirks(device_t);
static void thunderx2_ahci_bar_quirk(device_t);
struct pci_host_generic_quirk_entry pci_host_generic_quirks[] =
{
{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, thunderx2_ahci_bar_quirk},
{0, 0, 0, 0, NULL}
};
struct pci_host_generic_block_entry pci_host_generic_blocked[] =
{
/* ThunderX2 AHCI on second socket */
{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, 0x80, 0x10},
{0, 0, 0, 0, 0, 0}
};
andrewUnsubmitted
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Why is this needed?

andrew: Why is this needed?
pdk_semihalf.comAuthorUnsubmitted
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Second socket have SATA controller on chip. It is not exposed on board, and have bad adresses (like SATA on first socket). Instead of fixing addresses we block it.

pdk_semihalf.com: Second socket have SATA controller on chip. It is not exposed on board, and have bad adresses…
int int
pci_host_generic_core_attach(device_t dev) pci_host_generic_core_attach(device_t dev)
{ {
struct generic_pcie_core_softc *sc; struct generic_pcie_core_softc *sc;
int error; int error;
int rid; int rid;
sc = device_get_softc(dev); sc = device_get_softc(dev);
Show All 37 Linespci_host_generic_core_attach(device_t dev)
} }
error = rman_init(&sc->io_rman); error = rman_init(&sc->io_rman);
if (error) { if (error) {
device_printf(dev, "rman_init() failed. error = %d\n", error); device_printf(dev, "rman_init() failed. error = %d\n", error);
return (error); return (error);
} }
pci_host_generic_apply_quirks(dev);
return (0); return (0);
} }
static void
pci_host_generic_apply_quirks(device_t dev)
{
struct pci_host_generic_quirk_entry *quirk;
quirk = pci_host_generic_quirks;
while (1) {
if (quirk->impl == 0)
break;
if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
quirk->impl, quirk->part, quirk->var, quirk->rev) &&
quirk->func != NULL)
quirk->func(dev);
quirk++;
}
}
static uint32_t static uint32_t
generic_pcie_read_config(device_t dev, u_int bus, u_int slot, generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes) u_int func, u_int reg, int bytes)
{ {
struct generic_pcie_core_softc *sc; struct generic_pcie_core_softc *sc;
bus_space_handle_t h; bus_space_handle_t h;
bus_space_tag_t t; bus_space_tag_t t;
uint64_t offset; uint64_t offset;
uint32_t data; uint32_t data;
struct pci_host_generic_block_entry *block;
if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
return (~0U); return (~0U);
block = pci_host_generic_blocked;
while (1) {
if (block->impl == 0)
break;
if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
block->impl, block->part, block->var, block->rev) &&
block->bus == bus && block->slot == slot)
return (~0);
block++;
}
sc = device_get_softc(dev); sc = device_get_softc(dev);
offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
t = sc->bst; t = sc->bst;
h = sc->bsh; h = sc->bsh;
switch (bytes) { switch (bytes) {
case 1: case 1:
▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Linesstatic device_method_t generic_pcie_methods[] = {
DEVMETHOD(pcib_read_config, generic_pcie_read_config), DEVMETHOD(pcib_read_config, generic_pcie_read_config),
DEVMETHOD(pcib_write_config, generic_pcie_write_config), DEVMETHOD(pcib_write_config, generic_pcie_write_config),
DEVMETHOD_END DEVMETHOD_END
}; };
DEFINE_CLASS_0(pcib, generic_pcie_core_driver, DEFINE_CLASS_0(pcib, generic_pcie_core_driver,
generic_pcie_methods, sizeof(struct generic_pcie_core_softc)); generic_pcie_methods, sizeof(struct generic_pcie_core_softc));
static void thunderx2_ahci_bar_quirk(device_t dev)
{
/*
* XXX:
* On ThunderX2, AHCI BAR2 address is wrong. It needs to precisely
* match the one described in datasheet. Fixup it unconditionally.
andrewUnsubmitted
Not Done
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Is there an erratum for this?

andrew: Is there an erratum for this?
pdk_semihalf.comAuthorUnsubmitted
Not Done
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There is no erratum. Without this quirk kernel is trying to access bad address.

pdk_semihalf.com: There is no erratum. Without this quirk kernel is trying to access bad address.
andrewUnsubmitted
Not Done
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Why is the kernel trying to access a bad address?

andrew: Why is the kernel trying to access a bad address?
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

Kernel is trying to attach ahci. Look at log (without quirk of course) below it contains aforementioned bad address:

ahci0: <AHCI SATA controller> mem 0x41d4100041d30000-0x41d4100041d3ffff,0x41d20000-0x41d2ffff at device 16.0 on pci0                
PDK: virtual=0xffff000165388000 size=65536 pa=41d20000                                                                              
PDK: virtual=0xffff000165398000 size=65536 pa=41d4100041d30000                                                                      
ahci0: PDK: msix_table_bar: 24                                                                                                      
ahci0: PDK: msix_table_res: 0xfffffd0001e25180                                                                                      
ahci0: attempting to allocate 4 MSI-X vectors (4 supported)                                                                         
ahci0: using IRQs 11-14 for MSI-X                                                                                                                                                                                                                                                                                               
panic: vm_fault_hold: fault on nofault entry, addr: 0xffff000165398000
pdk_semihalf.com: Kernel is trying to attach ahci. Look at log (without quirk of course) below it contains…
*/
if (device_get_unit(dev) == 0) {
device_printf(dev, "running AHCI BAR fixup\n");
PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x18, 0x01440000, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x1c, 0x40, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x18, 0x01450000, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x1c, 0x40, 4);
}
}
andrewUnsubmitted
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Shouldn't you be getting this from the ACPI mcfg table?

andrew: Shouldn't you be getting this from the ACPI mcfg table?
pdk_semihalf.comAuthorUnsubmitted
Not Done
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Yes, I should get this from MCFG, but it doesn't provide information about pci on second socket. Furthermore segment passed to acpi_enable_pcie is 0 in both cases.

pdk_semihalf.com: Yes, I should get this from MCFG, but it doesn't provide information about pci on second socket.
andrewUnsubmitted
Not Done
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Will this always be unit 16, or would it be better to look at other information to detect when it's an ecam device.

andrew: Will this always be unit 16, or would it be better to look at other information to detect when…
pdk_semihalf.comAuthorUnsubmitted
Not Done
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It will be always unit 16. I've checked it once again and I have an idea. I will use _BBN to get ecam number. I'll update patches today so stay tuned.

pdk_semihalf.com: It will be always unit 16. I've checked it once again and I have an idea. I will use _BBN to…
View Options

usr.sbin/rpc.statd/statd.c

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
#define PCIE_REG_MASK 0xFFF #define PCIE_REG_MASK 0xFFF
#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
(((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
((reg) & PCIE_REG_MASK)) ((reg) & PCIE_REG_MASK))
typedef void (*pci_host_generic_quirk_function)(device_t);
struct pci_host_generic_quirk_entry {
int impl;
int part;
int var;
int rev;
pci_host_generic_quirk_function func;
};
struct pci_host_generic_block_entry {
int impl;
int part;
int var;
int rev;
int bus;
int slot;
};
/* Forward prototypes */ /* Forward prototypes */
static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes); u_int func, u_int reg, int bytes);
static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, uint32_t val, int bytes); u_int func, u_int reg, uint32_t val, int bytes);
static int generic_pcie_maxslots(device_t dev); static int generic_pcie_maxslots(device_t dev);
static int generic_pcie_read_ivar(device_t dev, device_t child, int index, static int generic_pcie_read_ivar(device_t dev, device_t child, int index,
uintptr_t *result); uintptr_t *result);
static int generic_pcie_write_ivar(device_t dev, device_t child, int index, static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
uintptr_t value); uintptr_t value);
static void pci_host_generic_apply_quirks(device_t);
static void thunderx2_ahci_bar_quirk(device_t);
struct pci_host_generic_quirk_entry pci_host_generic_quirks[] =
{
{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, thunderx2_ahci_bar_quirk},
{0, 0, 0, 0, NULL}
};
struct pci_host_generic_block_entry pci_host_generic_blocked[] =
{
/* ThunderX2 AHCI on second socket */
{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, 0x80, 0x10},
{0, 0, 0, 0, 0, 0}
};
andrewUnsubmitted
Not Done
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Why is this needed?

andrew: Why is this needed?
pdk_semihalf.comAuthorUnsubmitted
Not Done
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Second socket have SATA controller on chip. It is not exposed on board, and have bad adresses (like SATA on first socket). Instead of fixing addresses we block it.

pdk_semihalf.com: Second socket have SATA controller on chip. It is not exposed on board, and have bad adresses…
int int
pci_host_generic_core_attach(device_t dev) pci_host_generic_core_attach(device_t dev)
{ {
struct generic_pcie_core_softc *sc; struct generic_pcie_core_softc *sc;
int error; int error;
int rid; int rid;
sc = device_get_softc(dev); sc = device_get_softc(dev);
Show All 37 Linespci_host_generic_core_attach(device_t dev)
} }
error = rman_init(&sc->io_rman); error = rman_init(&sc->io_rman);
if (error) { if (error) {
device_printf(dev, "rman_init() failed. error = %d\n", error); device_printf(dev, "rman_init() failed. error = %d\n", error);
return (error); return (error);
} }
pci_host_generic_apply_quirks(dev);
return (0); return (0);
} }
static void
pci_host_generic_apply_quirks(device_t dev)
{
struct pci_host_generic_quirk_entry *quirk;
quirk = pci_host_generic_quirks;
while (1) {
if (quirk->impl == 0)
break;
if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
quirk->impl, quirk->part, quirk->var, quirk->rev) &&
quirk->func != NULL)
quirk->func(dev);
quirk++;
}
}
static uint32_t static uint32_t
generic_pcie_read_config(device_t dev, u_int bus, u_int slot, generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes) u_int func, u_int reg, int bytes)
{ {
struct generic_pcie_core_softc *sc; struct generic_pcie_core_softc *sc;
bus_space_handle_t h; bus_space_handle_t h;
bus_space_tag_t t; bus_space_tag_t t;
uint64_t offset; uint64_t offset;
uint32_t data; uint32_t data;
struct pci_host_generic_block_entry *block;
if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
return (~0U); return (~0U);
block = pci_host_generic_blocked;
while (1) {
if (block->impl == 0)
break;
if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
block->impl, block->part, block->var, block->rev) &&
block->bus == bus && block->slot == slot)
return (~0);
block++;
}
sc = device_get_softc(dev); sc = device_get_softc(dev);
offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
t = sc->bst; t = sc->bst;
h = sc->bsh; h = sc->bsh;
switch (bytes) { switch (bytes) {
case 1: case 1:
▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Linesstatic device_method_t generic_pcie_methods[] = {
DEVMETHOD(pcib_read_config, generic_pcie_read_config), DEVMETHOD(pcib_read_config, generic_pcie_read_config),
DEVMETHOD(pcib_write_config, generic_pcie_write_config), DEVMETHOD(pcib_write_config, generic_pcie_write_config),
DEVMETHOD_END DEVMETHOD_END
}; };
DEFINE_CLASS_0(pcib, generic_pcie_core_driver, DEFINE_CLASS_0(pcib, generic_pcie_core_driver,
generic_pcie_methods, sizeof(struct generic_pcie_core_softc)); generic_pcie_methods, sizeof(struct generic_pcie_core_softc));
static void thunderx2_ahci_bar_quirk(device_t dev)
{
/*
* XXX:
* On ThunderX2, AHCI BAR2 address is wrong. It needs to precisely
* match the one described in datasheet. Fixup it unconditionally.
andrewUnsubmitted
Not Done
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Is there an erratum for this?

andrew: Is there an erratum for this?
pdk_semihalf.comAuthorUnsubmitted
Not Done
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There is no erratum. Without this quirk kernel is trying to access bad address.

pdk_semihalf.com: There is no erratum. Without this quirk kernel is trying to access bad address.
andrewUnsubmitted
Not Done
Inline Actions

Why is the kernel trying to access a bad address?

andrew: Why is the kernel trying to access a bad address?
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

Kernel is trying to attach ahci. Look at log (without quirk of course) below it contains aforementioned bad address:

ahci0: <AHCI SATA controller> mem 0x41d4100041d30000-0x41d4100041d3ffff,0x41d20000-0x41d2ffff at device 16.0 on pci0                
PDK: virtual=0xffff000165388000 size=65536 pa=41d20000                                                                              
PDK: virtual=0xffff000165398000 size=65536 pa=41d4100041d30000                                                                      
ahci0: PDK: msix_table_bar: 24                                                                                                      
ahci0: PDK: msix_table_res: 0xfffffd0001e25180                                                                                      
ahci0: attempting to allocate 4 MSI-X vectors (4 supported)                                                                         
ahci0: using IRQs 11-14 for MSI-X                                                                                                                                                                                                                                                                                               
panic: vm_fault_hold: fault on nofault entry, addr: 0xffff000165398000
pdk_semihalf.com: Kernel is trying to attach ahci. Look at log (without quirk of course) below it contains…
*/
if (device_get_unit(dev) == 0) {
device_printf(dev, "running AHCI BAR fixup\n");
PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x18, 0x01440000, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x1c, 0x40, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x18, 0x01450000, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x1c, 0x40, 4);
}
}
andrewUnsubmitted
Not Done
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Shouldn't you be getting this from the ACPI mcfg table?

andrew: Shouldn't you be getting this from the ACPI mcfg table?
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

Yes, I should get this from MCFG, but it doesn't provide information about pci on second socket. Furthermore segment passed to acpi_enable_pcie is 0 in both cases.

pdk_semihalf.com: Yes, I should get this from MCFG, but it doesn't provide information about pci on second socket.
andrewUnsubmitted
Not Done
Inline Actions

Will this always be unit 16, or would it be better to look at other information to detect when it's an ecam device.

andrew: Will this always be unit 16, or would it be better to look at other information to detect when…
pdk_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

It will be always unit 16. I've checked it once again and I have an idea. I will use _BBN to get ecam number. I'll update patches today so stay tuned.

pdk_semihalf.com: It will be always unit 16. I've checked it once again and I have an idea. I will use _BBN to…