Codex is flagging this. I don't have the context to understand the referenced doc, but I'm sure you do. I know there were several cases where you said there were doc vs actual skew.

Fetch page sizes are counted without translation validity — lines 218–219 decode the page-size field unconditionally. AMD specifies that it is valid only when IBS_FETCH_CTL_PHYSADDRVALID is set. A focused test confirmed that an invalid translation still increments the page-size distribution. Apply that validity check. See AMD’s register reference, page 145 (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/56255_OSRR.pdf#page=145).

Codex is flagging this. I don't have the context to understand the referenced doc, but I'm sure you do. I know there were several cases where you said there were doc vs actual skew.

Load-latency statistics include invalid measurements — lines 244–246 add IbsDcMissLat for every load, including L1 hits. This measures cache-miss latency; AMD also explicitly excludes prefetch instructions. Including these samples corrupts the minimum, average, and distribution. Require a qualifying load miss and exclude prefetches. See AMD’s register reference, page 148 (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/56255_OSRR.pdf#page=148).

line 347 calls opstats.ldlat.average() whenever any Op samples exist. A trace containing only branches or stores leaves that histogram empty, causing integer division by zero.

codex says it reproduced SIGFPE with one branch sample.