Getting a couple conflicts after D55251 landed

Have rebased to main. Thanks!

I tried this on 3 EPYC generations at Netflix. The most recent (AMD EPYC 8434P, AMD EPYC 9535) behaved as expected. There was an dev.hwpstate_amd. node for each CPU, and a lot more freqs were exposed (from 3 to roughly a dozen).
On the oldest EPYC we have is EPYC 7502P, where it didn't change anything. We still only have 3 frequencies exposed. On this machine, we see just a single node from dev.hwpstate:
dev.hwpstate_amd.0.freq_settings: 2500/2750 2200/2200 1500/1350
dev.hwpstate_amd.0.%iommu:
dev.hwpstate_amd.0.%parent: cpu0
dev.hwpstate_amd.0.%pnpinfo:
dev.hwpstate_amd.0.%location:
dev.hwpstate_amd.0.%driver: hwpstate_amd
dev.hwpstate_amd.0.%desc: Cool`n'Quiet 2.0
dev.hwpstate_amd.%parent:

That contrasts to the other machines were we see something like this:

dev.hwpstate_amd.0.freq_settings: 400/-1 522/-1 644/-1 766/-1 888/-1 1010/-1 1132/-1 1255/-1 1377/-1 1499/-1 1621/-1 1743/-1 1865/-1 1987/-1 2110/-1 2232/-1 2354/-1 2476/-1 2598/-1 2720/-1 2843/-1 2965/-1 3087/-1
dev.hwpstate_amd.0.desired_performance: 33
dev.hwpstate_amd.0.maximum_performance: 255
dev.hwpstate_amd.0.minimum_performance: 33
dev.hwpstate_amd.0.epp: 0
dev.hwpstate_amd.0.%iommu:
dev.hwpstate_amd.0.%parent: cpu0
dev.hwpstate_amd.0.%pnpinfo:
dev.hwpstate_amd.0.%location:
dev.hwpstate_amd.0.%driver: hwpstate_amd
dev.hwpstate_amd.0.%desc: AMD Collaborative Processor Performance Control (CPPC)

I'm assuming its a BIOS setting to enable hwpstate, but I don't see it anywhere..

More generally, my assumption is that powerd is in complete control here, as it would be without the hwpstate control (which is great, as its exactly what I want). If somebody wanted to use EPP, I guess you'd poke at dev.hwpstate_amd.0.epp ?

All in all, this looks great. It seems to do no harm on the older box, and exposes more control for powerd on the newer boxes!