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Differential D47255

x86/iommu/amd_reg.h: AMD IOMMU registers definitions
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Authored by kib on Oct 22 2024, 8:21 PM.

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rG0a9bec17447c: x86/iommu/amd_reg.h: AMD IOMMU registers definitions

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kib created this revision.Oct 22 2024, 8:21 PM

Herald added a subscriber: imp. · View Herald TranscriptOct 22 2024, 8:21 PM

kib requested review of this revision.Oct 22 2024, 8:21 PM

kib added a child revision: D47256: AMD IOMMU driver.

emaste added inline comments.Oct 27 2024, 5:23 PM

sys/x86/iommu/amd_reg.h
306–307	These are 16 bits are they not?
687	there's a reserved bit missing between vnr and vevent?

Fix several mistakes in re-typing

I've now looked through all the structs except amdiommu_cmd_generic and amdiommu_event_generic. I've only done a spot-check of the #defines, did not find any issues yet.

sys/x86/iommu/amd_reg.h
393	missing reserved bits between dest and vector?
637	is there missing padding before op here? also maybe I'm looking at a spec with a typo as it suggests op is 5 bits for reset_vmmio

kib marked an inline comment as done.Oct 28 2024, 1:07 AM

kib added inline comments.

sys/x86/iommu/amd_reg.h
393	This is from fig. 15 (table 20) on page 89, rev. 3.09. Can you point out the bits numbers for the reserved field you mean there?
637	It is op and rsrv2 which should be swapped.

emaste added inline comments.Oct 28 2024, 1:22 AM

sys/x86/iommu/amd_reg.h
393	Hmm, I guess I was looking at a vapic case somehow

I looked over the structs and spot-checked some #defines.

This revision is now accepted and ready to land.Fri, Nov 1, 2:33 PM

Closed by commit rG0a9bec17447c: x86/iommu/amd_reg.h: AMD IOMMU registers definitions (authored by kib). · Explain WhySat, Nov 2, 11:47 PM

This revision was automatically updated to reflect the committed changes.

kib marked an inline comment as done.

kib added a commit: rG0a9bec17447c: x86/iommu/amd_reg.h: AMD IOMMU registers definitions.

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sys/x86/iommu/amd_reg.h

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