x86/iommu/amd_reg.h: AMD IOMMU registers definitions

[emaste]

sys/x86/iommu/amd_reg.h

306–307

These are 16 bits are they not?

687

there's a reserved bit missing between vnr and vevent?

[kib]

Fix several mistakes in re-typing

[emaste]

I've now looked through all the structs except amdiommu_cmd_generic and amdiommu_event_generic. I've only done a spot-check of the #defines, did not find any issues yet.

sys/x86/iommu/amd_reg.h

393

missing reserved bits between dest and vector?

637

is there missing padding before op here?

also maybe I'm looking at a spec with a typo as it suggests op is 5 bits for reset_vmmio

[kib]

sys/x86/iommu/amd_reg.h

393

This is from fig. 15 (table 20) on page 89, rev. 3.09.

Can you point out the bits numbers for the reserved field you mean there?

637

It is op and rsrv2 which should be swapped.

[emaste]

sys/x86/iommu/amd_reg.h

393

Hmm, I guess I was looking at a vapic case somehow

[emaste]

I looked over the structs and spot-checked some #defines.