The main interrupt controller of the D1 is the PLIC, but it does not
provide any interface for configuring IRQ trigger type or wakeup.
These features are supported through registers in a separate memory
region (RISCV_CFG), and the device tree defines another interrupt
controller (INTC) as a wrapper around the PLIC and those registers.
Since most peripherals use INTC as their interrupt parent, and do not
use IRQ trigger type or wakeup features, do the following:
- add the D1 compatible data to the PLIC driver,
- add a stub driver for INTC to route things back to the PLIC.
Signed-off-by: Julien Cassette <julien.cassette@gmail.com>
fsync needs to be added here, or an ahci-hd file-backed disk image will fail on FreeBSD guest shutdown with
(ada0:ahcich0:0:0:0): FLUSHCACHE48. ACB: ea 00 00 00 00 40 00 00 00 00 00 00
(ada0:ahcich0:0:0:0): CAM status: ATA Status Error
(ada0:ahcich0:0:0:0): ATA status: 41 (DRDY ERR), error: 04 (ABRT )
(ada0:ahcich0:0:0:0): RES: 41 04 00 00 00 40 00 00 00 00 00
(ada0:ahcich0:0:0:0): Retrying command
(ada0:ahcich0:0:0:0): FLUSHCACHE48. ACB: ea 00 00 00 00 40 00 00 00 00 00 00
(ada0:ahcich0:0:0:0): CAM status: ATA Status Error
(ada0:ahcich0:0:0:0): ATA status: 41 (DRDY ERR), error: 04 (ABRT )
(ada0:ahcich0:0:0:0): RES: 41 04 00 00 00 40 00 00 00 00 00
(ada0:ahcich0:0:0:0): Error 5, Retries exhausted
(ada0:ahcich0:0:0:0): Synchronize cache failed
#ifndef WITHOUT_CAPSICUM
+ cap_rights_init(&rights, CAP_IOCTL, CAP_READ, CAP_SEEK, CAP_WRITE,
+ CAP_FSYNC);
+ if (ro) {
+ cap_rights_clear(&rights, CAP_FSYNC);
+ }