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riscv rust stdarch
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Authored by jrtc27 on Nov 7 2021, 5:30 PM.
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F31620627: riscv stdarch
Nov 7 2021, 5:30 PM
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diff --git a/crates/std_detect/src/detect/os/freebsd/auxvec.rs b/crates/std_detect/src/detect/os/freebsd/auxvec.rs
index f12476ad..29fcc8cb 100644
--- a/crates/std_detect/src/detect/os/freebsd/auxvec.rs
+++ b/crates/std_detect/src/detect/os/freebsd/auxvec.rs
@@ -3,7 +3,8 @@
any(
target_arch = "aarch64",
target_arch = "arm",
- target_arch = "powerpc64"
+ target_arch = "powerpc64",
+ target_arch = "riscv64"
),
allow(dead_code)
)]

Event Timeline

jrtc27 created this paste.Nov 7 2021, 5:30 PM
jrtc27 created this object in space S1 Global.
jrtc27 changed the title of this paste from riscv stdarch to riscv rust stdarch.
jrtc27 mentioned this in D32881: WIP: lang/rust: Add riscv64gc-unknown-freebsd target.Nov 7 2021, 5:37 PM