[PATCH 1/7] clk/allwinner: fixes and the A64 display clocks

[vice-shore-grid_duck.com]

Summary

Changes to the Allwinner clock drivers needed to run the A64 display
pipeline (DE2 mixer, TCON0, MIPI DSI, D-PHY), two of them plain bugs
that affect any consumer of the clocks involved.

[manu]

Please upload diff with full context.

sys/dev/clk/allwinner/ccu_a64.c

662

tcon0 is cleary a MUX clock, why would you change this ? (See 3.3.5.42. TCON0 Clock Register from the A64 User Manual)

728

parent 01 is invalid for dsi, so it should be : {"pll_video0", NULL, "pll_periph0"}
Other part seems correct

[vice-shore-grid_duck.com]

Fix context size + dsi_dphy_parents definition.

[vice-shore-grid_duck.com]

sys/dev/clk/allwinner/ccu_a64.c

662

That's because it's gated, so clk_enable has no effect on it, so it remains in the state that the firmware left it - which on the PineTab is "disabled".

Now, I'm aware that there is a similar pattern with e.g. i2s, where there's a MUX_CLK and a CCU_GATE construction, and the gate child carries the id. But the device tree dtb (inherited from Linux and/or u-boot) assigns the parents to the mux. Then when clk_set_assigned is called, it gets the gate node, looks for pll_mipi which isn't a parent node of the gate, but of the mux. So it can't find the parent.

What I can do, is either create a MUX_GATE_CLK macro for this specific use case, or add a more detailed comment explaining the issue and keep using `M_CLK. Unless you have a better suggestion?