Previously the attach() tries to find the functional/interface/... clocks that is assigned to ti_sysc node in the FDT. if the necessary clocks are not yet created that will fail, but the driver couldnt just fail to attach because the child nodes has the clocks, so accept it and attach the children. After a while it will try again to find the clocks in the bus_new_pass phase.
Remove that solution becuase it take a long time to sort things out and the ti_sysc is in some middle state during that time.
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