Initial import of Ralink/Mediatek MIPS SoC support #3

[sgalabov]

Summary

Interrupt controllers found in various Mediatek/Ralink SoCs.
mtk_intr_v1 and mtk_intr_v2 are basically the same at the moment, with just different register mappings.
However, v1 interrupt controller has a subset of the functionality of the v2 interrupt controller, so in the future the v2 interrupt controller driver may be enhanced, if needed, with things like level/edge interrupts and soft interrupts. So, for the moment I suggest we keep them as 2 separate files.
mtk_intr_gic provides very basic (similar to v1 and v2) support for MIPS GIC controllers, which currently maps all interrupts to a single core and sets them to type level, active high. In the future this may be developed into a generic GIC controller to support any new MIPS SoCs that include it. The GIC is a standard MTI interrupt controller in their multi-core line-up (e.g., 1004K, 1074K, etc.), rather than a SoC-specific controller.

[sgalabov]

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