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Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction for clearing hazards
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Authored by Sgalabov_gmail.com on Jan 26 2016, 10:47 AM.

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Summary

This revision makes currently known MIPS32 Release 2 and Release 3 CPUs use the EHB instruction when clearing hazards. So far the MIPS 74K and MIPS1004K (somewhat) were already using the EHB. Now we add more r2 and r3 CPUs to this list.

Also, for the cases of MIPS coherent processing systems (currently 1004K, 1074K, interAptiv and proAptiv) - define proper CCA attributes.

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Sgalabov_gmail.com retitled this revision from to Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction for clearing hazards.
Sgalabov_gmail.com updated this object.
Sgalabov_gmail.com edited the test plan for this revision. (Show Details)
Sgalabov_gmail.com added reviewers: MIPS, imp, adrian.
Sgalabov_gmail.com set the repository for this revision to rS FreeBSD src repository - subversion.
Sgalabov_gmail.com added a project: MIPS.

Backed out the sys/mips/include/asm.h change as it is probably too risky at the moment.

imp edited edge metadata.
This revision is now accepted and ready to land.Jan 27 2016, 6:05 AM
Sgalabov_gmail.com edited edge metadata.

After discussion with imp@, removed the CPU_MIPS24KE option, as 24KE is not really different than 24K, apart from having DSP ASE, which can be detected dynamically via Config3 register.

This revision now requires review to proceed.Jan 27 2016, 7:48 AM
This revision was automatically updated to reflect the committed changes.