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Differential D43874

kboot: Add our own lua bindings
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Authored by imp on Feb 13 2024, 11:38 PM.
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Reviewers
manu
kevans
Commits
rG78f5850093c5: kboot: Add our own lua bindings
rGe34fd722cafe: kboot: Add our own lua bindings
Summary

Create a small wrapper around the new flua hash module so we can use it
here too. There's no 4th bindings, nor will they be created.

Sponsored by: Netflix

Diff Detail

Repository
rG FreeBSD src repository
Lint
Lint Not Applicable
Unit
Tests Not Applicable

Event Timeline

imp created this revision.Feb 13 2024, 11:38 PM
Herald added a reviewer: manu. · View Herald TranscriptFeb 13 2024, 11:38 PM
Herald added a subscriber: dab. · View Herald Transcript
imp requested review of this revision.Feb 13 2024, 11:38 PM
Harbormaster completed remote builds in B55996: Diff 134278.Feb 13 2024, 11:38 PM
imp updated this revision to Diff 134279.Feb 13 2024, 11:39 PM

Add bindings for hash functions.

Harbormaster completed remote builds in B55997: Diff 134279.Feb 13 2024, 11:39 PM
imp added a reviewer: kevans.Feb 13 2024, 11:39 PM
imp updated this revision to Diff 134283.Feb 14 2024, 5:28 AM

redo the build.
bump the limit on bios for a little bit.

Harbormaster completed remote builds in B56000: Diff 134283.Feb 14 2024, 5:28 AM
imp added inline comments.Feb 14 2024, 5:38 AM
stand/i386/loader/Makefile
36

This will be omitted

This revision was not accepted when it landed; it landed in state Needs Review.Feb 16 2024, 4:01 AM
Closed by commit rGe34fd722cafe: kboot: Add our own lua bindings (authored by imp). · Explain Why
This revision was automatically updated to reflect the committed changes.
imp added a commit: rGe34fd722cafe: kboot: Add our own lua bindings.
imp added a commit: rG78f5850093c5: kboot: Add our own lua bindings.Apr 16 2024, 8:14 PM

Revision Contents
Changeset List

PathSize
stand/
1 line
i386/
loader/
2 lines
kboot/
kboot/
7 lines
19 lines
liblua/
3 lines

Diff 134419

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stand/defs.mk

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
/* /*
* Reported Temperature Control Register * Reported Temperature Control Register
*/ */
#define AMDTEMP_REPTMP_CTRL 0xa4 #define AMDTEMP_REPTMP_CTRL 0xa4
/* /*
* Reported Temperature, Family 17h * Reported Temperature, Family 17h
*
* According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
* provide the current temp. bit 19, when clear, means the temp is reported in
* a range 0.."225C" (probable typo for 255C), and when set changes the range
* to -49..206C.
*/ */
#define AMDTEMP_17H_CUR_TMP 0x59800 #define AMDTEMP_17H_CUR_TMP 0x59800
#define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1 << 19)
#define AMDTEMP_17H_CUR_TMP_RANGE_OFF 490
/* /*
* Thermaltrip Status Register (Family 0Fh only) * Thermaltrip Status Register (Family 0Fh only)
*/ */
#define AMDTEMP_THERMTP_STAT 0xe4 #define AMDTEMP_THERMTP_STAT 0xe4
#define AMDTEMP_TTSR_SELCORE 0x04 #define AMDTEMP_TTSR_SELCORE 0x04
#define AMDTEMP_TTSR_SELSENSOR 0x40 #define AMDTEMP_TTSR_SELSENSOR 0x40
▲ Show 20 Lines • Show All 462 Lines • ▼ Show 20 Linesamdtemp_gettemp(device_t dev, amdsensor_t sensor)
return (temp); return (temp);
} }
static int32_t static int32_t
amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) amdtemp_gettemp17h(device_t dev, amdsensor_t sensor)
{ {
struct amdtemp_softc *sc = device_get_softc(dev); struct amdtemp_softc *sc = device_get_softc(dev);
uint32_t temp; uint32_t temp, val;
int error; int error;
error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &temp); error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val);
KASSERT(error == 0, ("amdsmn_read")); KASSERT(error == 0, ("amdsmn_read"));
temp = ((temp >> 21) & 0x7ff) * 5 / 4; temp = ((val >> 21) & 0x7ff) * 5 / 4;
if ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0)
temp -= AMDTEMP_17H_CUR_TMP_RANGE_OFF;
temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10; temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10;
return (temp); return (temp);
} }
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stand/i386/loader/Makefile

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
/* /*
* Reported Temperature Control Register * Reported Temperature Control Register
*/ */
#define AMDTEMP_REPTMP_CTRL 0xa4 #define AMDTEMP_REPTMP_CTRL 0xa4
/* /*
* Reported Temperature, Family 17h * Reported Temperature, Family 17h
*
* According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
* provide the current temp. bit 19, when clear, means the temp is reported in
* a range 0.."225C" (probable typo for 255C), and when set changes the range
* to -49..206C.
*/ */
#define AMDTEMP_17H_CUR_TMP 0x59800 #define AMDTEMP_17H_CUR_TMP 0x59800
#define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1 << 19)
#define AMDTEMP_17H_CUR_TMP_RANGE_OFF 490
/* /*
* Thermaltrip Status Register (Family 0Fh only) * Thermaltrip Status Register (Family 0Fh only)
*/ */
#define AMDTEMP_THERMTP_STAT 0xe4 #define AMDTEMP_THERMTP_STAT 0xe4
#define AMDTEMP_TTSR_SELCORE 0x04 #define AMDTEMP_TTSR_SELCORE 0x04
#define AMDTEMP_TTSR_SELSENSOR 0x40 #define AMDTEMP_TTSR_SELSENSOR 0x40
▲ Show 20 Lines • Show All 462 Lines • ▼ Show 20 Linesamdtemp_gettemp(device_t dev, amdsensor_t sensor)
return (temp); return (temp);
} }
static int32_t static int32_t
amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) amdtemp_gettemp17h(device_t dev, amdsensor_t sensor)
{ {
struct amdtemp_softc *sc = device_get_softc(dev); struct amdtemp_softc *sc = device_get_softc(dev);
uint32_t temp; uint32_t temp, val;
int error; int error;
error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &temp); error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val);
KASSERT(error == 0, ("amdsmn_read")); KASSERT(error == 0, ("amdsmn_read"));
temp = ((temp >> 21) & 0x7ff) * 5 / 4; temp = ((val >> 21) & 0x7ff) * 5 / 4;
if ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0)
temp -= AMDTEMP_17H_CUR_TMP_RANGE_OFF;
temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10; temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10;
return (temp); return (temp);
} }
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stand/kboot/kboot/Makefile

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
/* /*
* Reported Temperature Control Register * Reported Temperature Control Register
*/ */
#define AMDTEMP_REPTMP_CTRL 0xa4 #define AMDTEMP_REPTMP_CTRL 0xa4
/* /*
* Reported Temperature, Family 17h * Reported Temperature, Family 17h
*
* According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
* provide the current temp. bit 19, when clear, means the temp is reported in
* a range 0.."225C" (probable typo for 255C), and when set changes the range
* to -49..206C.
*/ */
#define AMDTEMP_17H_CUR_TMP 0x59800 #define AMDTEMP_17H_CUR_TMP 0x59800
#define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1 << 19)
#define AMDTEMP_17H_CUR_TMP_RANGE_OFF 490
/* /*
* Thermaltrip Status Register (Family 0Fh only) * Thermaltrip Status Register (Family 0Fh only)
*/ */
#define AMDTEMP_THERMTP_STAT 0xe4 #define AMDTEMP_THERMTP_STAT 0xe4
#define AMDTEMP_TTSR_SELCORE 0x04 #define AMDTEMP_TTSR_SELCORE 0x04
#define AMDTEMP_TTSR_SELSENSOR 0x40 #define AMDTEMP_TTSR_SELSENSOR 0x40
▲ Show 20 Lines • Show All 462 Lines • ▼ Show 20 Linesamdtemp_gettemp(device_t dev, amdsensor_t sensor)
return (temp); return (temp);
} }
static int32_t static int32_t
amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) amdtemp_gettemp17h(device_t dev, amdsensor_t sensor)
{ {
struct amdtemp_softc *sc = device_get_softc(dev); struct amdtemp_softc *sc = device_get_softc(dev);
uint32_t temp; uint32_t temp, val;
int error; int error;
error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &temp); error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val);
KASSERT(error == 0, ("amdsmn_read")); KASSERT(error == 0, ("amdsmn_read"));
temp = ((temp >> 21) & 0x7ff) * 5 / 4; temp = ((val >> 21) & 0x7ff) * 5 / 4;
if ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0)
temp -= AMDTEMP_17H_CUR_TMP_RANGE_OFF;
temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10; temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10;
return (temp); return (temp);
} }
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stand/kboot/kboot/lua_bindings.c

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
/* /*
* Reported Temperature Control Register * Reported Temperature Control Register
*/ */
#define AMDTEMP_REPTMP_CTRL 0xa4 #define AMDTEMP_REPTMP_CTRL 0xa4
/* /*
* Reported Temperature, Family 17h * Reported Temperature, Family 17h
*
* According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
* provide the current temp. bit 19, when clear, means the temp is reported in
* a range 0.."225C" (probable typo for 255C), and when set changes the range
* to -49..206C.
*/ */
#define AMDTEMP_17H_CUR_TMP 0x59800 #define AMDTEMP_17H_CUR_TMP 0x59800
#define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1 << 19)
#define AMDTEMP_17H_CUR_TMP_RANGE_OFF 490
/* /*
* Thermaltrip Status Register (Family 0Fh only) * Thermaltrip Status Register (Family 0Fh only)
*/ */
#define AMDTEMP_THERMTP_STAT 0xe4 #define AMDTEMP_THERMTP_STAT 0xe4
#define AMDTEMP_TTSR_SELCORE 0x04 #define AMDTEMP_TTSR_SELCORE 0x04
#define AMDTEMP_TTSR_SELSENSOR 0x40 #define AMDTEMP_TTSR_SELSENSOR 0x40
▲ Show 20 Lines • Show All 462 Lines • ▼ Show 20 Linesamdtemp_gettemp(device_t dev, amdsensor_t sensor)
return (temp); return (temp);
} }
static int32_t static int32_t
amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) amdtemp_gettemp17h(device_t dev, amdsensor_t sensor)
{ {
struct amdtemp_softc *sc = device_get_softc(dev); struct amdtemp_softc *sc = device_get_softc(dev);
uint32_t temp; uint32_t temp, val;
int error; int error;
error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &temp); error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val);
KASSERT(error == 0, ("amdsmn_read")); KASSERT(error == 0, ("amdsmn_read"));
temp = ((temp >> 21) & 0x7ff) * 5 / 4; temp = ((val >> 21) & 0x7ff) * 5 / 4;
if ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0)
temp -= AMDTEMP_17H_CUR_TMP_RANGE_OFF;
temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10; temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10;
return (temp); return (temp);
} }
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stand/liblua/Makefile

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