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Add support for unspecified ranges on ARM64 ThunderX system
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Authored by wma_semihalf.com on Oct 1 2015, 6:09 AM.

Details

Summary
When one is trying to allocate a resource with unspecified range,
read already configured BAR values (by UEFI or whatever).
This is necessary to make VFs working and to allow them to be
properly allocated.

Diff Detail

Repository
rS FreeBSD src repository
Lint
Automatic diff as part of commit; lint not applicable.
Unit
Automatic diff as part of commit; unit tests not applicable.

Event Timeline

wma_semihalf.com retitled this revision from to Add support for unspecified ranges on ARM64 ThunderX system.
wma_semihalf.com updated this object.
wma_semihalf.com edited the test plan for this revision. (Show Details)
wma_semihalf.com added a reviewer: arm64.
wma_semihalf.com set the repository for this revision to rS FreeBSD src repository.
zbb accepted this revision.Oct 1 2015, 7:38 PM
zbb added a reviewer: zbb.
This revision is now accepted and ready to land.Oct 1 2015, 7:38 PM
andrew added inline comments.Oct 1 2015, 7:56 PM
sys/arm64/cavium/thunder_pcie.c
102 ↗(On Diff #8994)

Why 4?

465 ↗(On Diff #8994)

What is happening here? I don't understand how this works, a comment would be useful to help explain it.

472 ↗(On Diff #8994)

You talk about 3 64-bit bars, then use 5 here. Why?

imp added a comment.Oct 4 2015, 9:49 PM

I think this is OK, but I don't know much about VF

sys/arm64/cavium/thunder_pcie.c
465 ↗(On Diff #8994)

You're supposed to write all f's to the BAR to size it. The bits for the decode lines will be 0's, the address range it occupies are 1's. So this flips the upper bits that are set and adds 1 to get the size. The masking above masks out the low-order bits that contain attributes for the mapping.

472 ↗(On Diff #8994)

0, 2 and 4 are valid valid values for 3 64-bit BARs. 5 is the first invalid one.

emaste added inline comments.Oct 15 2015, 6:25 PM
sys/arm64/cavium/thunder_pcie.c
472 ↗(On Diff #8994)

Alternatively, 6 is the 4th 64-bit BAR?

sys/arm64/cavium/thunder_pcie.c
472 ↗(On Diff #8994)

PCI supports up to 6 BAR registers. They can be used either as 6x 32-bit regs, or 3x 64-bit. Anyway, PCIR_BAR(5) is the last valid entry inside configuration header, so anything above means we're accessing VFs.

wma_semihalf.com edited edge metadata.
This revision now requires review to proceed.Oct 23 2015, 10:54 AM
This revision was automatically updated to reflect the committed changes.