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stand: common devparse
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Authored by imp on Nov 8 2022, 10:49 PM.
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Sponsored by: Netflix

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Build 45121: arc lint + arc unit

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stand/
efi/
libefi/
112 lines
libsa/
82 lines
2 lines

Diff 112789

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stand/efi/libefi/devicename.c

Show First 20 Lines • Show All 1,366 Lines • ▼ Show 20 Linesstatic struct ef10_external_port_map_s {
* SFN7xx4F (Pavia): * SFN7xx4F (Pavia):
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 2 * port 1 -> cage 2
* port 2 -> cage 3 * port 2 -> cage 3
* port 3 -> cage 4 * port 3 -> cage 4
*/ */
{ {
EFX_FAMILY_HUNTINGTON, EFX_FAMILY_HUNTINGTON,
(1 << TLV_PORT_MODE_10G) | (1U << TLV_PORT_MODE_10G) | /* mode 0 */
(1 << TLV_PORT_MODE_10G_10G) | (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
(1 << TLV_PORT_MODE_10G_10G_10G_10G), (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1, 1, /* ports per cage */
1 1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate each port number to a separate * Modes that on Medford allocate each port number to a separate
* cage. * cage.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 2 * port 1 -> cage 2
* port 2 -> cage 3 * port 2 -> cage 3
* port 3 -> cage 4 * port 3 -> cage 4
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G) | (1U << TLV_PORT_MODE_10G) | /* mode 0 */
(1 << TLV_PORT_MODE_10G_10G), (1U << TLV_PORT_MODE_10G_10G), /* mode 2 */
1, 1, /* ports per cage */
1 1 /* first cage */
}, },
/* /*
* Modes which for Huntington identify a chip variant where 2 * Modes which for Huntington identify a chip variant where 2
* adjacent port numbers map to each cage. * adjacent port numbers map to each cage.
* SFN7x42Q (Monza): * SFN7x42Q (Monza):
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 1 * port 1 -> cage 1
* port 2 -> cage 2 * port 2 -> cage 2
* port 3 -> cage 2 * port 3 -> cage 2
*/ */
{ {
EFX_FAMILY_HUNTINGTON, EFX_FAMILY_HUNTINGTON,
(1 << TLV_PORT_MODE_40G) | (1U << TLV_PORT_MODE_40G) | /* mode 1 */
(1 << TLV_PORT_MODE_40G_40G) | (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
(1 << TLV_PORT_MODE_40G_10G_10G) | (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
(1 << TLV_PORT_MODE_10G_10G_40G), (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
2, 2, /* ports per cage */
1 1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 2 adjacent port numbers to each * Modes that on Medford allocate 2 adjacent port numbers to each
* cage. * cage.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 1 * port 1 -> cage 1
* port 2 -> cage 2 * port 2 -> cage 2
* port 3 -> cage 2 * port 3 -> cage 2
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_40G) | (1U << TLV_PORT_MODE_40G) | /* mode 1 */
(1 << TLV_PORT_MODE_40G_40G) | (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
(1 << TLV_PORT_MODE_40G_10G_10G) | (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
(1 << TLV_PORT_MODE_10G_10G_40G) | (1U << TLV_PORT_MODE_10G_10G_40G) | /* mode 7 */
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
2, (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1 2, /* ports per cage */
1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 4 adjacent port numbers to each * Modes that on Medford allocate 4 adjacent port numbers to each
* connector, starting on cage 1. * connector, starting on cage 1.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 1 * port 1 -> cage 1
* port 2 -> cage 1 * port 2 -> cage 1
* port 3 -> cage 1 * port 3 -> cage 1
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) | (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q) | /* mode 5 */
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
4, (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* mode 4 */
1, 4, /* ports per cage */
1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 4 adjacent port numbers to each * Modes that on Medford allocate 4 adjacent port numbers to each
* connector, starting on cage 2. * connector, starting on cage 2.
* port 0 -> cage 2 * port 0 -> cage 2
* port 1 -> cage 2 * port 1 -> cage 2
* port 2 -> cage 2 * port 2 -> cage 2
* port 3 -> cage 2 * port 3 -> cage 2
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2), (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q2), /* mode 8 */
4, 4, /* ports per cage */
2 2 /* first cage */
}, },
}; };
static __checkReturn efx_rc_t static __checkReturn efx_rc_t
ef10_external_port_mapping( ef10_external_port_mapping(
__in efx_nic_t *enp, __in efx_nic_t *enp,
__in uint32_t port, __in uint32_t port,
__out uint8_t *external_portp) __out uint8_t *external_portp)
▲ Show 20 Lines • Show All 760 Lines • Show Last 20 Lines
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stand/libsa/dev.c

Show First 20 Lines • Show All 1,366 Lines • ▼ Show 20 Linesstatic struct ef10_external_port_map_s {
* SFN7xx4F (Pavia): * SFN7xx4F (Pavia):
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 2 * port 1 -> cage 2
* port 2 -> cage 3 * port 2 -> cage 3
* port 3 -> cage 4 * port 3 -> cage 4
*/ */
{ {
EFX_FAMILY_HUNTINGTON, EFX_FAMILY_HUNTINGTON,
(1 << TLV_PORT_MODE_10G) | (1U << TLV_PORT_MODE_10G) | /* mode 0 */
(1 << TLV_PORT_MODE_10G_10G) | (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
(1 << TLV_PORT_MODE_10G_10G_10G_10G), (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1, 1, /* ports per cage */
1 1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate each port number to a separate * Modes that on Medford allocate each port number to a separate
* cage. * cage.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 2 * port 1 -> cage 2
* port 2 -> cage 3 * port 2 -> cage 3
* port 3 -> cage 4 * port 3 -> cage 4
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G) | (1U << TLV_PORT_MODE_10G) | /* mode 0 */
(1 << TLV_PORT_MODE_10G_10G), (1U << TLV_PORT_MODE_10G_10G), /* mode 2 */
1, 1, /* ports per cage */
1 1 /* first cage */
}, },
/* /*
* Modes which for Huntington identify a chip variant where 2 * Modes which for Huntington identify a chip variant where 2
* adjacent port numbers map to each cage. * adjacent port numbers map to each cage.
* SFN7x42Q (Monza): * SFN7x42Q (Monza):
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 1 * port 1 -> cage 1
* port 2 -> cage 2 * port 2 -> cage 2
* port 3 -> cage 2 * port 3 -> cage 2
*/ */
{ {
EFX_FAMILY_HUNTINGTON, EFX_FAMILY_HUNTINGTON,
(1 << TLV_PORT_MODE_40G) | (1U << TLV_PORT_MODE_40G) | /* mode 1 */
(1 << TLV_PORT_MODE_40G_40G) | (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
(1 << TLV_PORT_MODE_40G_10G_10G) | (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
(1 << TLV_PORT_MODE_10G_10G_40G), (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
2, 2, /* ports per cage */
1 1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 2 adjacent port numbers to each * Modes that on Medford allocate 2 adjacent port numbers to each
* cage. * cage.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 1 * port 1 -> cage 1
* port 2 -> cage 2 * port 2 -> cage 2
* port 3 -> cage 2 * port 3 -> cage 2
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_40G) | (1U << TLV_PORT_MODE_40G) | /* mode 1 */
(1 << TLV_PORT_MODE_40G_40G) | (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
(1 << TLV_PORT_MODE_40G_10G_10G) | (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
(1 << TLV_PORT_MODE_10G_10G_40G) | (1U << TLV_PORT_MODE_10G_10G_40G) | /* mode 7 */
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
2, (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1 2, /* ports per cage */
1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 4 adjacent port numbers to each * Modes that on Medford allocate 4 adjacent port numbers to each
* connector, starting on cage 1. * connector, starting on cage 1.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 1 * port 1 -> cage 1
* port 2 -> cage 1 * port 2 -> cage 1
* port 3 -> cage 1 * port 3 -> cage 1
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) | (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q) | /* mode 5 */
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
4, (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* mode 4 */
1, 4, /* ports per cage */
1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 4 adjacent port numbers to each * Modes that on Medford allocate 4 adjacent port numbers to each
* connector, starting on cage 2. * connector, starting on cage 2.
* port 0 -> cage 2 * port 0 -> cage 2
* port 1 -> cage 2 * port 1 -> cage 2
* port 2 -> cage 2 * port 2 -> cage 2
* port 3 -> cage 2 * port 3 -> cage 2
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2), (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q2), /* mode 8 */
4, 4, /* ports per cage */
2 2 /* first cage */
}, },
}; };
static __checkReturn efx_rc_t static __checkReturn efx_rc_t
ef10_external_port_mapping( ef10_external_port_mapping(
__in efx_nic_t *enp, __in efx_nic_t *enp,
__in uint32_t port, __in uint32_t port,
__out uint8_t *external_portp) __out uint8_t *external_portp)
▲ Show 20 Lines • Show All 760 Lines • Show Last 20 Lines
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stand/libsa/stand.h

Show First 20 Lines • Show All 1,366 Lines • ▼ Show 20 Linesstatic struct ef10_external_port_map_s {
* SFN7xx4F (Pavia): * SFN7xx4F (Pavia):
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 2 * port 1 -> cage 2
* port 2 -> cage 3 * port 2 -> cage 3
* port 3 -> cage 4 * port 3 -> cage 4
*/ */
{ {
EFX_FAMILY_HUNTINGTON, EFX_FAMILY_HUNTINGTON,
(1 << TLV_PORT_MODE_10G) | (1U << TLV_PORT_MODE_10G) | /* mode 0 */
(1 << TLV_PORT_MODE_10G_10G) | (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
(1 << TLV_PORT_MODE_10G_10G_10G_10G), (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1, 1, /* ports per cage */
1 1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate each port number to a separate * Modes that on Medford allocate each port number to a separate
* cage. * cage.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 2 * port 1 -> cage 2
* port 2 -> cage 3 * port 2 -> cage 3
* port 3 -> cage 4 * port 3 -> cage 4
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G) | (1U << TLV_PORT_MODE_10G) | /* mode 0 */
(1 << TLV_PORT_MODE_10G_10G), (1U << TLV_PORT_MODE_10G_10G), /* mode 2 */
1, 1, /* ports per cage */
1 1 /* first cage */
}, },
/* /*
* Modes which for Huntington identify a chip variant where 2 * Modes which for Huntington identify a chip variant where 2
* adjacent port numbers map to each cage. * adjacent port numbers map to each cage.
* SFN7x42Q (Monza): * SFN7x42Q (Monza):
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 1 * port 1 -> cage 1
* port 2 -> cage 2 * port 2 -> cage 2
* port 3 -> cage 2 * port 3 -> cage 2
*/ */
{ {
EFX_FAMILY_HUNTINGTON, EFX_FAMILY_HUNTINGTON,
(1 << TLV_PORT_MODE_40G) | (1U << TLV_PORT_MODE_40G) | /* mode 1 */
(1 << TLV_PORT_MODE_40G_40G) | (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
(1 << TLV_PORT_MODE_40G_10G_10G) | (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
(1 << TLV_PORT_MODE_10G_10G_40G), (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
2, 2, /* ports per cage */
1 1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 2 adjacent port numbers to each * Modes that on Medford allocate 2 adjacent port numbers to each
* cage. * cage.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 1 * port 1 -> cage 1
* port 2 -> cage 2 * port 2 -> cage 2
* port 3 -> cage 2 * port 3 -> cage 2
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_40G) | (1U << TLV_PORT_MODE_40G) | /* mode 1 */
(1 << TLV_PORT_MODE_40G_40G) | (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
(1 << TLV_PORT_MODE_40G_10G_10G) | (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
(1 << TLV_PORT_MODE_10G_10G_40G) | (1U << TLV_PORT_MODE_10G_10G_40G) | /* mode 7 */
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
2, (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1 2, /* ports per cage */
1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 4 adjacent port numbers to each * Modes that on Medford allocate 4 adjacent port numbers to each
* connector, starting on cage 1. * connector, starting on cage 1.
* port 0 -> cage 1 * port 0 -> cage 1
* port 1 -> cage 1 * port 1 -> cage 1
* port 2 -> cage 1 * port 2 -> cage 1
* port 3 -> cage 1 * port 3 -> cage 1
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) | (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q) | /* mode 5 */
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
4, (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* mode 4 */
1, 4, /* ports per cage */
1 /* first cage */
}, },
/* /*
* Modes that on Medford allocate 4 adjacent port numbers to each * Modes that on Medford allocate 4 adjacent port numbers to each
* connector, starting on cage 2. * connector, starting on cage 2.
* port 0 -> cage 2 * port 0 -> cage 2
* port 1 -> cage 2 * port 1 -> cage 2
* port 2 -> cage 2 * port 2 -> cage 2
* port 3 -> cage 2 * port 3 -> cage 2
*/ */
{ {
EFX_FAMILY_MEDFORD, EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2), (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q2), /* mode 8 */
4, 4, /* ports per cage */
2 2 /* first cage */
}, },
}; };
static __checkReturn efx_rc_t static __checkReturn efx_rc_t
ef10_external_port_mapping( ef10_external_port_mapping(
__in efx_nic_t *enp, __in efx_nic_t *enp,
__in uint32_t port, __in uint32_t port,
__out uint8_t *external_portp) __out uint8_t *external_portp)
▲ Show 20 Lines • Show All 760 Lines • Show Last 20 Lines