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Add Cavium ThunderX xHCI controller PCI ID
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Authored by emaste on Sep 14 2015, 7:37 PM.
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Summary

See P74 for the full pciconf -lv from the system

none1@pci0:0:16:0:      class=0x0c0330 card=0xa11b177d chip=0xa01b177d rev=0x01 hdr=0x00
    vendor     = 'Cavium, Inc.'
    device     = 'THUNDERX xHCI USB Controller'
    class      = serial bus
    subclass   = USB
none2@pci0:0:17:0:      class=0x0c0330 card=0xa11b177d chip=0xa01b177d rev=0x01 hdr=0x00
    vendor     = 'Cavium, Inc.'
    device     = 'THUNDERX xHCI USB Controller'
    class      = serial bus
 subclass = USB

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emaste retitled this revision from to Add Cavium ThunderX xHCI controller PCI ID.
emaste updated this object.
emaste edited the test plan for this revision. (Show Details)
emaste added a reviewer: hselasky.
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You are sure this device does not need any port routing quirks?

This revision is now accepted and ready to land.Sep 14 2015, 7:39 PM
sys/dev/usb/controller/xhci_pci.c
116–118 ↗(On Diff #8755)

One question - the sorting here is going to get awkward as we add more xHCI controllers. Should we sort alphabetically by mfgr name and then by device_id? We do want all of the mfgr entries to remain together I'd say, so sorting just by device_id is insufficient. Sorting by "lower 16 bytes of device_id then by upper 16 bits" would work but is awkward.

sys/dev/usb/controller/xhci_pci.c
116–118 ↗(On Diff #8755)

The compiler usually sorts the entries, though sorting first by the lower 16-bits then the higher 16-bits is fine by me. This should be done as a separate commit. It would be really cool if these PCI strings were provided the PCI space, instead of by hand :-)

--HPS

The compiler usually sorts the entries, though sorting first by the lower 16-bits then the higher 16-bits is fine by me.

Right, I'm just talking about sorting for code maintainability. It will get to be a real mess if we have entries ending up in arbitrary order.

This revision was automatically updated to reflect the committed changes.