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Support PL-connected Ethernet on Zynq platforms.
Needs ReviewPublic

Authored by skibo on Mar 27 2020, 10:20 PM.

Details

Reviewers
None
Group Reviewers
ARM
Summary

The Zynq SLCR block assumes the Ethernet refernence clock is always sourced
from the IO_PLL. But, to put an Ethernet PHY design in the PL (FPGA) often
requires the reference clock to come from the PL instead. This fix allows
the Ethernet clock to come from any PLL as well as from the PL (via EMIO).
In the case of EMIO sourced clock, the clock dividers are ignored and it
is assumed the PL adjusts the clock frequency when the media changes.

Test Plan

I don't have access to a design with Ethernet connected to the PL. But, I
have tested that the change doesn't affect the more common case of
Ethernet connected to the PS.

Diff Detail

Repository
rS FreeBSD src repository - subversion
Lint
Lint OK
Unit
No Unit Test Coverage
Build Status
Buildable 30142
Build 27948: arc lint + arc unit