fix riscv load/stores
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Authored by br on Jan 17 2020, 4:11 PM.

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imp

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jrtc27

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rS356834: Use unsigned loads in fubyte, fuword16, generic_bs_r_1, generic_bs_r_2

Summary

Use unsigned load/stores as these functions should do zero-extend

Test Plan

these bugs discovered by running pci_read_cap()

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br created this revision.Jan 17 2020, 4:11 PM

Yes, this is exactly what I had in mind.

This revision is now accepted and ready to land.Jan 17 2020, 4:14 PM

Closed by commit rS356834: Use unsigned loads in fubyte, fuword16, generic_bs_r_1, generic_bs_r_2 (authored by br). · Explain WhyJan 17 2020, 4:48 PM

This revision was automatically updated to reflect the committed changes.

br added a commit: rS356834: Use unsigned loads in fubyte, fuword16, generic_bs_r_1, generic_bs_r_2.

Herald added a subscriber: imp. · View Herald TranscriptJan 17 2020, 4:48 PM

Revision Contents
Changeset List

Path

Size

sys/

riscv/

bus_space_asm.S

4 lines

support.S

4 lines

Diff 66915

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sys/riscv/riscv/bus_space_asm.S