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markj

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rS347514: Add support for HiFive Unleashed -- the board with a multi-core RISC-V SoC

Summary

Pick a hart to boot on using hart lottery. This is an official RISC-V way to avoid booting on the management hart used in Linux. Management hart runs BBL initialization sequence and it releases main CPUs before it jumps to FreeBSD entry point itself. So it never wins the lottery.
Renumber CPUs early on boot so we can boot on any hart.

This fixes operation on HiFive Unleashed.

Test Plan

Tested in QEMU and HiFive Unleashed.

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Repository

rS FreeBSD src repository - subversion

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Tests Not Applicable

Event Timeline

br created this revision.May 10 2019, 2:55 PM

Fix !SMP build.

emaste added a subscriber: emaste.May 10 2019, 6:40 PM

Store hart in struct pcpu
Store harts not CPUIDs in pmap->pm_active

Use all_harts mask in release_aps()

Fix bug: use CPU_FILL to fill up kernel pmap pm_active.
all_harts is not initialized yet in pmap_boostrap()

markj added inline comments.May 11 2019, 4:28 PM

sys/riscv/riscv/mp_machdep.c
398 ↗	(On Diff #57314)	Hmm. Looks like Linux assumes that hartIDs can fit in a cpuset. I guess we can assume that too, but IMO we should assert that hartids are < MAXCPU.
sys/riscv/riscv/pmap.c
4295 ↗	(On Diff #57314)	The var should be called "hart", ditto elsewhere.

Assert that hart < MAXCPU
Rename cpu variable to hart

markj accepted this revision.May 12 2019, 1:08 AM

This revision is now accepted and ready to land.May 12 2019, 1:08 AM

Closed by commit rS347514: Add support for HiFive Unleashed -- the board with a multi-core RISC-V SoC (authored by br). · Explain WhyMay 12 2019, 4:17 PM

This revision was automatically updated to reflect the committed changes.

Herald added a subscriber: imp. · View Herald TranscriptMay 12 2019, 4:17 PM

HiFive Unleashed support
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Diff 57339

head/sys/riscv/include/pcpu.h

head/sys/riscv/riscv/intr_machdep.c

head/sys/riscv/riscv/locore.S

head/sys/riscv/riscv/machdep.c

head/sys/riscv/riscv/mp_machdep.c

head/sys/riscv/riscv/pmap.c

HiFive Unleashed supportClosedPublicActions

Details

Diff Detail

Event Timeline

Revision ContentsChangeset List

Diff 57339

head/sys/riscv/include/pcpu.h

head/sys/riscv/riscv/intr_machdep.c

head/sys/riscv/riscv/locore.S

head/sys/riscv/riscv/machdep.c

head/sys/riscv/riscv/mp_machdep.c

head/sys/riscv/riscv/pmap.c

HiFive Unleashed support
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Revision Contents
Changeset List