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amd64: fix BUS_SPACE_MAXSIZE to 64bit max value.
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Authored by kib on May 4 2019, 9:55 AM.
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I think that 4G value for BUS_SPACE_MAXSIZE still chomped the PCIe max DMA transfers into 4G chunks.

In D20154#434058, @kib wrote:

I think that 4G value for BUS_SPACE_MAXSIZE still chomped the PCIe max DMA transfers into 4G chunks.

I don't see the PCI driver interposing a tag between the driver and the nexus bounce or DMAR drivers. Plus, empirically after I removed the 4GB boundary requirement the ioat(4) driver was able to issue > 4GB requests without segmentation forced on it. Since ioat(4) passes it's own device specific maxsize, it's immune to this change.

This change looks good to me. Thanks for taking care of this!

This revision is now accepted and ready to land.May 4 2019, 11:05 AM
jhb added inline comments.
sys/x86/include/bus.h
116 ↗(On Diff #57031)

I would maybe keep it next to the MAXSIZE_<xx>BIT constants where it was before. That is how the MAXADDR constants are arranged.

This revision was automatically updated to reflect the committed changes.