Remove p_code from struct proc.

[jhb]

Summary

Contrary to the comments, it was never used by core dumps or debuggers.
Instead, it used to hold the signal code of a pending signal, but that
was replaced by the 'ksi_code' member of ksiginfo_t when signal information
was reworked in 7.0.

Test Plan

• compiled and booted amd64 and i386 kernels and ran ptrace_test under both

sys/kern/kern_sig.c

 
 /*
  * Set CESA decode windows.
  */
 static void
 decode_win_cesa_setup(u_long base)
 {
         uint32_t br, cr;
+        uint64_t size;
         int i, j;
 
         for (i = 0; i < MV_WIN_CESA_MAX; i++) {
                 win_cesa_cr_write(base, i, 0);
                 win_cesa_br_write(base, i, 0);
         }
 
         /* Only access to active DRAM banks is required */
         for (i = 0; i < MV_WIN_DDR_MAX; i++) {
                 if (ddr_is_active(i)) {
                         br = ddr_base(i);
 
-                        cr = (((ddr_size(i) - 1) & 0xffff0000) |
+                        size = ddr_size(i);
+#ifdef SOC_MV_ARMADA38X
+                        /*
+                         * Armada 38x SoC's equipped with 4GB DRAM
+                         * suffer freeze during CESA operation, if
+                         * MBUS window opened at given DRAM CS reaches
+                         * end of the address space. Apply a workaround
+                         * by setting the window size to the closest possible
+                         * value, i.e. divide it by 2.
+                         */
+                        if (size + ddr_base(i) == 0x100000000ULL)
+                                size /= 2;
+#endif
+
+                        cr = (((size - 1) & 0xffff0000) |
                             (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
                             (ddr_target(i) << IO_WIN_TGT_SHIFT) |
                             IO_WIN_ENA_MASK);
 
                         /* Set the first free CESA window */
                         for (j = 0; j < MV_WIN_CESA_MAX; j++) {
                                 if (win_cesa_cr_read(base, j) & 0x1)
                                         continue;

sys/kern/kern_thread.c

 
 /*
  * Set CESA decode windows.
  */
 static void
 decode_win_cesa_setup(u_long base)
 {
         uint32_t br, cr;
+        uint64_t size;
         int i, j;
 
         for (i = 0; i < MV_WIN_CESA_MAX; i++) {
                 win_cesa_cr_write(base, i, 0);
                 win_cesa_br_write(base, i, 0);
         }
 
         /* Only access to active DRAM banks is required */
         for (i = 0; i < MV_WIN_DDR_MAX; i++) {
                 if (ddr_is_active(i)) {
                         br = ddr_base(i);
 
-                        cr = (((ddr_size(i) - 1) & 0xffff0000) |
+                        size = ddr_size(i);
+#ifdef SOC_MV_ARMADA38X
+                        /*
+                         * Armada 38x SoC's equipped with 4GB DRAM
+                         * suffer freeze during CESA operation, if
+                         * MBUS window opened at given DRAM CS reaches
+                         * end of the address space. Apply a workaround
+                         * by setting the window size to the closest possible
+                         * value, i.e. divide it by 2.
+                         */
+                        if (size + ddr_base(i) == 0x100000000ULL)
+                                size /= 2;
+#endif
+
+                        cr = (((size - 1) & 0xffff0000) |
                             (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
                             (ddr_target(i) << IO_WIN_TGT_SHIFT) |
                             IO_WIN_ENA_MASK);
 
                         /* Set the first free CESA window */
                         for (j = 0; j < MV_WIN_CESA_MAX; j++) {
                                 if (win_cesa_cr_read(base, j) & 0x1)
                                         continue;

sys/sys/proc.h

 
 /*
  * Set CESA decode windows.
  */
 static void
 decode_win_cesa_setup(u_long base)
 {
         uint32_t br, cr;
+        uint64_t size;
         int i, j;
 
         for (i = 0; i < MV_WIN_CESA_MAX; i++) {
                 win_cesa_cr_write(base, i, 0);
                 win_cesa_br_write(base, i, 0);
         }
 
         /* Only access to active DRAM banks is required */
         for (i = 0; i < MV_WIN_DDR_MAX; i++) {
                 if (ddr_is_active(i)) {
                         br = ddr_base(i);
 
-                        cr = (((ddr_size(i) - 1) & 0xffff0000) |
+                        size = ddr_size(i);
+#ifdef SOC_MV_ARMADA38X
+                        /*
+                         * Armada 38x SoC's equipped with 4GB DRAM
+                         * suffer freeze during CESA operation, if
+                         * MBUS window opened at given DRAM CS reaches
+                         * end of the address space. Apply a workaround
+                         * by setting the window size to the closest possible
+                         * value, i.e. divide it by 2.
+                         */
+                        if (size + ddr_base(i) == 0x100000000ULL)
+                                size /= 2;
+#endif
+
+                        cr = (((size - 1) & 0xffff0000) |
                             (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
                             (ddr_target(i) << IO_WIN_TGT_SHIFT) |
                             IO_WIN_ENA_MASK);
 
                         /* Set the first free CESA window */
                         for (j = 0; j < MV_WIN_CESA_MAX; j++) {
                                 if (win_cesa_cr_read(base, j) & 0x1)
                                         continue;