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cxgbe: Fix false sharing between t4_nm_intr and cxgbe_netmap_rxsync
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Authored by bwicht_verisign.com on Nov 6 2018, 1:23 PM.
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np
Summary

Split sge_nm_rxq fields into three cachelines.

Submitted by: Marc De La Gueronniere <mdelagueronniere@verisign.com>
MFC after: 1 week
Sponsored by: Verisign, Inc.

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Build 20092: arc lint + arc unit

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np requested changes to this revision.Nov 6 2018, 5:34 PM

How about using __aligned(CACHE_LINE_SIZE) like the rest of the driver and let the compiler figure out the padding?

This revision now requires changes to proceed.Nov 6 2018, 5:34 PM

Use __aligned(CACHE_LINE_SIZE) instead of manual padding

In D17869#381863, @np wrote:

How about using __aligned(CACHE_LINE_SIZE) like the rest of the driver and let the compiler figure out the padding?

Excellent idea!

I just did the change.

Thanks, Navdeep.

Can you please try r359159?